X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=ff73e1a12ac6f5d0f953d9c9f9a9439ebe7f2375;hb=a3f35e348e535c2610e67390d466f49c3f0d9f42;hp=ba974eb975184ca1ba969c471b265d355dae1c79;hpb=11ef6e64856eef2f7ad09af83128a78c01e01cf7;p=openocd.git

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index ba974eb975..ff73e1a12a 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -49,10 +49,12 @@ int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *c
 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm926ejs_quit();
-int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size);
+int arm926ejs_arch_state(struct target_s *target);
 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int arm926ejs_soft_reset_halt(struct target_s *target);
+static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
+static int arm926ejs_mmu(struct target_s *target, int *enabled);
 
 target_type_t arm926ejs_target =
 {
@@ -89,7 +91,9 @@ target_type_t arm926ejs_target =
 	.register_commands = arm926ejs_register_commands,
 	.target_command = arm926ejs_target_command,
 	.init_target = arm926ejs_init_target,
-	.quit = arm926ejs_quit
+	.quit = arm926ejs_quit,
+	.virt2phys = arm926ejs_virt2phys,
+	.mmu = arm926ejs_mmu
 };
 
 
@@ -169,7 +173,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 	fields[3].in_handler = NULL;
 	fields[3].in_handler_priv = NULL;
 	
-	jtag_add_dr_scan(4, fields, -1, NULL);
+	jtag_add_dr_scan(4, fields, -1);
 
 	fields[0].in_handler_priv = value;
 	fields[0].in_handler = arm_jtag_buf_to_u32;
@@ -179,7 +183,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 		/* rescan with NOP, to wait for the access to complete */
 		access = 0;
 		nr_w_buf = 0;
-		jtag_add_dr_scan(4, fields, -1, NULL);
+		jtag_add_dr_scan(4, fields, -1);
 		jtag_execute_queue();
 	} while (buf_get_u32(&access, 0, 1) != 1);
 
@@ -251,14 +255,14 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
 	fields[3].in_handler = NULL;
 	fields[3].in_handler_priv = NULL;
 	
-	jtag_add_dr_scan(4, fields, -1, NULL);
+	jtag_add_dr_scan(4, fields, -1);
 
 	do
 	{
 		/* rescan with NOP, to wait for the access to complete */
 		access = 0;
 		nr_w_buf = 0;
-		jtag_add_dr_scan(4, fields, -1, NULL);
+		jtag_add_dr_scan(4, fields, -1);
 		jtag_execute_queue();
 	} while (buf_get_u32(&access, 0, 1) != 1);
 
@@ -333,9 +337,11 @@ int arm926ejs_examine_debug_reason(target_t *target)
 		default:
 			ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
 			target->debug_reason = DBG_REASON_DBGRQ;
+			retval = ERROR_TARGET_FAILURE;
+			break;
 	}
 	
-	return ERROR_OK;
+	return retval;
 }
 
 u32 arm926ejs_get_ttb(target_t *target)
@@ -530,7 +536,7 @@ int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p,
 	return ERROR_OK;
 }
 
-int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size)
+int arm926ejs_arch_state(struct target_s *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -548,7 +554,7 @@ int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size)
 		exit(-1);
 	}
 	
-	snprintf(buf, buf_size,
+	USER(
 			"target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8x pc: 0x%8.8x\n"
 			"MMU: %s, D-Cache: %s, I-Cache: %s",
@@ -698,6 +704,7 @@ int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char
 	int chain_pos;
 	char *variant = NULL;
 	arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
+	memset(arm926ejs, 0, sizeof(*arm926ejs));
 	
 	if (argc < 4)
 	{
@@ -899,3 +906,42 @@ int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char
 	
 	return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 }
+static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
+{
+	int retval;
+	int type;
+	u32 cb;
+	int domain;
+	u32 ap;
+	
+	armv4_5_common_t *armv4_5;
+	arm7_9_common_t *arm7_9;
+	arm9tdmi_common_t *arm9tdmi;
+	arm926ejs_common_t *arm926ejs;
+	retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
+	if (retval != ERROR_OK)
+	{
+		return retval;
+	}
+	u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
+	if (type == -1)
+	{
+		return ret;
+	}
+	*physical = ret;
+	return ERROR_OK;
+}
+
+static int arm926ejs_mmu(struct target_s *target, int *enabled)
+{
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
+	
+	if (target->state != TARGET_HALTED)
+	{
+		ERROR("Target not halted");
+		return ERROR_TARGET_INVALID;
+	}
+	*enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
+	return ERROR_OK;
+}