X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=f05087e471db5a33942a6e7e9204bcfe0f9c4be9;hb=57bc9f37c9029f1b481cd50e15676a0f74aa9e92;hp=2a3ba3071f1be52717b7c22b29c9584b4658121c;hpb=0e0d887cd617b35b894732f4314434f3a51493d0;p=openocd.git

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 2a3ba3071f..f05087e471 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -34,8 +34,6 @@
 #endif
 
 /* cli handling */
-int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
-
 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -50,10 +48,8 @@ int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *c
 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int arm926ejs_quit(void);
-int arm926ejs_arch_state(struct target_s *target);
 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int arm926ejs_soft_reset_halt(struct target_s *target);
+
 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
 static int arm926ejs_mmu(struct target_s *target, int *enabled);
 
@@ -98,9 +94,12 @@ target_type_t arm926ejs_target =
 	.mmu = arm926ejs_mmu
 };
 
-
 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
 {
+	/* FIX!!!! this code should be reenabled. For now it does not check
+	 * the queue...*/
+	return 0;
+#if 0
 	/* The ARM926EJ-S' instruction register is 4 bits wide */
 	u8 t = *captured & 0xf;
 	u8 t2 = *field->in_check_value & 0xf;
@@ -114,6 +113,7 @@ int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
 		return ERROR_OK;
 	}
 	return ERROR_JTAG_QUEUE_FAILED;;
+#endif
 }
 
 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
@@ -132,57 +132,40 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 
 	buf_set_u32(address_buf, 0, 14, address);
 
-	jtag_add_end_state(TAP_RTI);
+	jtag_add_end_state(TAP_IDLE);
 	if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 	{
 		return retval;
 	}
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
-	fields[0].device = jtag_info->chain_pos;
+	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
-	fields[0].out_mask = NULL;
-	fields[0].in_value = NULL;
-	fields[0].in_check_value = NULL;
-	fields[0].in_check_mask = NULL;
-	fields[0].in_handler = NULL;
-	fields[0].in_handler_priv = NULL;
+	u8 tmp[4];
+	fields[0].in_value = tmp;
+
 
-	fields[1].device = jtag_info->chain_pos;
+	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 1;
 	fields[1].out_value = &access;
-	fields[1].out_mask = NULL;
 	fields[1].in_value = &access;
-	fields[1].in_check_value = NULL;
-	fields[1].in_check_mask = NULL;
-	fields[1].in_handler = NULL;
-	fields[1].in_handler_priv = NULL;
 
-	fields[2].device = jtag_info->chain_pos;
+
+	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 14;
 	fields[2].out_value = address_buf;
-	fields[2].out_mask = NULL;
 	fields[2].in_value = NULL;
-	fields[2].in_check_value = NULL;
-	fields[2].in_check_mask = NULL;
-	fields[2].in_handler = NULL;
-	fields[2].in_handler_priv = NULL;
 
-	fields[3].device = jtag_info->chain_pos;
+
+
+	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
-	fields[3].out_mask = NULL;
 	fields[3].in_value = NULL;
-	fields[3].in_check_value = NULL;
-	fields[3].in_check_mask = NULL;
-	fields[3].in_handler = NULL;
-	fields[3].in_handler_priv = NULL;
 
-	jtag_add_dr_scan(4, fields, -1);
 
-	fields[0].in_handler_priv = value;
-	fields[0].in_handler = arm_jtag_buf_to_u32;
+	jtag_add_dr_scan(4, fields, TAP_INVALID);
 
 	/*TODO: add timeout*/
 	do
@@ -190,7 +173,10 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
 		/* rescan with NOP, to wait for the access to complete */
 		access = 0;
 		nr_w_buf = 0;
-		jtag_add_dr_scan(4, fields, -1);
+		jtag_add_dr_scan_now(4, fields, TAP_INVALID);
+
+		*value=le_to_h_u32(tmp);
+
 		if((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
@@ -222,61 +208,61 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
 	buf_set_u32(address_buf, 0, 14, address);
 	buf_set_u32(value_buf, 0, 32, value);
 
-	jtag_add_end_state(TAP_RTI);
+	jtag_add_end_state(TAP_IDLE);
 	if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 	{
 		return retval;
 	}
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
-	fields[0].device = jtag_info->chain_pos;
+	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = value_buf;
-	fields[0].out_mask = NULL;
+
 	fields[0].in_value = NULL;
-	fields[0].in_check_value = NULL;
-	fields[0].in_check_mask = NULL;
-	fields[0].in_handler = NULL;
-	fields[0].in_handler_priv = NULL;
 
-	fields[1].device = jtag_info->chain_pos;
+
+
+
+
+	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 1;
 	fields[1].out_value = &access;
-	fields[1].out_mask = NULL;
+
 	fields[1].in_value = &access;
-	fields[1].in_check_value = NULL;
-	fields[1].in_check_mask = NULL;
-	fields[1].in_handler = NULL;
-	fields[1].in_handler_priv = NULL;
 
-	fields[2].device = jtag_info->chain_pos;
+
+
+
+
+	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 14;
 	fields[2].out_value = address_buf;
-	fields[2].out_mask = NULL;
+
 	fields[2].in_value = NULL;
-	fields[2].in_check_value = NULL;
-	fields[2].in_check_mask = NULL;
-	fields[2].in_handler = NULL;
-	fields[2].in_handler_priv = NULL;
 
-	fields[3].device = jtag_info->chain_pos;
+
+
+
+
+	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
-	fields[3].out_mask = NULL;
+
 	fields[3].in_value = NULL;
-	fields[3].in_check_value = NULL;
-	fields[3].in_check_mask = NULL;
-	fields[3].in_handler = NULL;
-	fields[3].in_handler_priv = NULL;
 
-	jtag_add_dr_scan(4, fields, -1);
+
+
+
+
+	jtag_add_dr_scan(4, fields, TAP_INVALID);
 	/*TODO: add timeout*/
 	do
 	{
 		/* rescan with NOP, to wait for the access to complete */
 		access = 0;
 		nr_w_buf = 0;
-		jtag_add_dr_scan(4, fields, -1);
+		jtag_add_dr_scan(4, fields, TAP_INVALID);
 		if((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
@@ -366,7 +352,7 @@ int arm926ejs_examine_debug_reason(target_t *target)
 		default:
 			LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
 			target->debug_reason = DBG_REASON_DBGRQ;
-			/* if we fail here, we won't talk to the target and it will 
+			/* if we fail here, we won't talk to the target and it will
 			 * be reported to be in the halted state */
 			retval = ERROR_TARGET_FAILURE;
 			break;
@@ -498,7 +484,6 @@ void arm926ejs_post_debug_entry(target_t *target)
 	LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
 		arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 
-
 	u32 cache_dbg_ctrl;
 
 	/* read-modify-write CP15 cache debug control register
@@ -666,7 +651,6 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
 	return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
-
 }
 
 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
@@ -705,23 +689,21 @@ int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
 	arm9tdmi_init_target(cmd_ctx, target);
 
 	return ERROR_OK;
-
 }
 
 int arm926ejs_quit(void)
 {
-
 	return ERROR_OK;
 }
 
-int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, const char *variant)
+int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
 {
 	arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
 	arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 
 	/* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 	 */
-	arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
+	arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 
 	arm9tdmi->arch_info = arm926ejs;
 	arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
@@ -755,7 +737,7 @@ int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
 {
 	arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
 
-	arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant);
+	arm926ejs_init_arch_info(target, arm926ejs, target->tap);
 
 	return ERROR_OK;
 }
@@ -945,6 +927,7 @@ int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char
 
 	return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 }
+
 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
 {
 	int retval;