X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=8a609b0762504e4711fa190d95a186b966ac25ed;hb=4d88f024a614f699d5ce5673520762bcfdf96ce2;hp=89fbfae3b05f52fc215e20dde4ac03df64f835ec;hpb=e8af4de0a7d224e1aa28e72f0de1ddf0bec5beb8;p=openocd.git

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 89fbfae3b0..8a609b0762 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -63,6 +63,8 @@ target_type_t arm926ejs_target =
 	.poll = arm7_9_poll,
 	.arch_state = arm926ejs_arch_state,
 
+	.target_request_data = arm7_9_target_request_data,
+
 	.halt = arm7_9_halt,
 	.resume = arm7_9_resume,
 	.step = arm7_9_step,
@@ -77,7 +79,8 @@ target_type_t arm926ejs_target =
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm926ejs_write_memory,
 	.bulk_write_memory = arm7_9_bulk_write_memory,
-
+	.checksum_memory = arm7_9_checksum_memory,
+	
 	.run_algorithm = armv4_5_run_algorithm,
 
 	.add_breakpoint = arm7_9_add_breakpoint,
@@ -91,20 +94,22 @@ target_type_t arm926ejs_target =
 	.quit = arm926ejs_quit
 };
 
-int arm926ejs_catch_broken_irscan(u8 *in_value, void *priv)
+
+int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
 {
 	/* The ARM926EJ-S' instruction register is 4 bits wide */
-	*in_value &= 0xf;
-	
-	if ((*in_value == 0x0f) || (*in_value == 0x00))
+	u8 t = *captured & 0xf;
+	u8 t2 = *field->in_check_value & 0xf;
+	if (t == t2)
 	{
-		DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
 		return ERROR_OK;
 	}
-	else
+	else if ((t == 0x0f) || (t == 0x00))
 	{
-		return ERROR_JTAG_QUEUE_FAILED;
+		DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
+		return ERROR_OK;
 	}
+	return ERROR_JTAG_QUEUE_FAILED;;
 }
 
 int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
@@ -116,7 +121,6 @@ int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
 	u8 address_buf[2];
 	u8 nr_w_buf = 0;
 	u8 access = 1;
-	error_handler_t error_handler;
 	
 	buf_set_u32(address_buf, 0, 14, address);
 	
@@ -181,11 +185,8 @@ int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	DEBUG("addr: 0x%x value: %8.8x", address, *value);
 #endif
-
-	error_handler.error_handler = arm926ejs_catch_broken_irscan;
-	error_handler.error_handler_priv = NULL;
 	
-	arm_jtag_set_instr(jtag_info, 0xc, &error_handler);
+	arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
 
 	return ERROR_OK;
 }
@@ -200,7 +201,6 @@ int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
 	u8 address_buf[2];
 	u8 nr_w_buf = 1;
 	u8 access = 1;
-	error_handler_t error_handler;
 	
 	buf_set_u32(address_buf, 0, 14, address);
 	buf_set_u32(value_buf, 0, 32, value);
@@ -264,10 +264,7 @@ int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
 	DEBUG("addr: 0x%x value: %8.8x", address, value);
 #endif
 
-	error_handler.error_handler = arm926ejs_catch_broken_irscan;
-	error_handler.error_handler_priv = NULL;
-	
-	arm_jtag_set_instr(jtag_info, 0xf, &error_handler);
+	arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
 
 	return ERROR_OK;
 }
@@ -477,7 +474,7 @@ void arm926ejs_pre_restore_context(target_t *target)
 	/* read-modify-write CP15 cache debug control register 
 	 * to reenable I/D-cache linefills and disable WT */
 	arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
-	cache_dbg_ctrl |= 0x7;
+	cache_dbg_ctrl &= ~0x7;
 	arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
 }