X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=329aa12a43c26eece14ebdad7c0d5989d513f6d6;hb=5f6962b34f623e7daf0dfb1f6249620431b5ab79;hp=aa2998905590aab453b14903389fa1c0e45ee00b;hpb=dd9894f481d127266c201d7075ecbdd34b034124;p=openocd.git

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index aa29989055..329aa12a43 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -56,7 +56,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 	uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 	struct scan_field fields[4];
-	uint8_t address_buf[2];
+	uint8_t address_buf[2] = {0, 0};
 	uint8_t nr_w_buf = 0;
 	uint8_t access = 1;
 
@@ -149,7 +149,7 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 	uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 	struct scan_field fields[4];
 	uint8_t value_buf[4];
-	uint8_t address_buf[2];
+	uint8_t address_buf[2] = {0, 0};
 	uint8_t nr_w_buf = 1;
 	uint8_t access = 1;
 
@@ -494,7 +494,7 @@ int arm926ejs_arch_state(struct target *target)
 	};
 
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
-	struct armv4_5_common_s *armv4_5;
+	struct arm *armv4_5;
 
 	if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
 	{
@@ -524,7 +524,7 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	int retval = ERROR_OK;
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
+	struct arm *armv4_5 = &arm7_9->armv4_5_common;
 	struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
 	if ((retval = target_halt(target)) != ERROR_OK)
@@ -713,67 +713,6 @@ static int arm926ejs_target_create(struct target *target, Jim_Interp *interp)
 	return arm926ejs_init_arch_info(target, arm926ejs, target->tap);
 }
 
-COMMAND_HANDLER(arm926ejs_handle_cp15_command)
-{
-	int retval;
-	struct target *target = get_current_target(CMD_CTX);
-	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
-	int opcode_1;
-	int opcode_2;
-	int CRn;
-	int CRm;
-
-	if ((CMD_ARGC < 4) || (CMD_ARGC > 5))
-	{
-		command_print(CMD_CTX, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
-		return ERROR_OK;
-	}
-
-	COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], opcode_1);
-	COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], opcode_2);
-	COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], CRn);
-	COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], CRm);
-
-	retval = arm926ejs_verify_pointer(CMD_CTX, arm926ejs);
-	if (retval != ERROR_OK)
-		return retval;
-
-	if (target->state != TARGET_HALTED)
-	{
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
-		return ERROR_OK;
-	}
-
-	if (CMD_ARGC == 4)
-	{
-		uint32_t value;
-		if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
-		{
-			command_print(CMD_CTX, "couldn't access register");
-			return ERROR_OK;
-		}
-		if ((retval = jtag_execute_queue()) != ERROR_OK)
-		{
-			return retval;
-		}
-
-		command_print(CMD_CTX, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
-	}
-	else
-	{
-		uint32_t value;
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], value);
-		if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
-		{
-			command_print(CMD_CTX, "couldn't access register");
-			return ERROR_OK;
-		}
-		command_print(CMD_CTX, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
-	}
-
-	return ERROR_OK;
-}
-
 COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
 {
 	int retval;
@@ -817,28 +756,31 @@ static int arm926ejs_mmu(struct target *target, int *enabled)
 	return ERROR_OK;
 }
 
+static const struct command_registration arm926ejs_exec_command_handlers[] = {
+	{
+		.name = "cache_info",
+		.handler = &arm926ejs_handle_cache_info_command,
+		.mode = COMMAND_EXEC,
+		.help = "display information about target caches",
+
+	},
+	COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration arm926ejs_command_handlers[] = {
+	{
+		.name = "arm926ejs",
+		.mode = COMMAND_ANY,
+		.help = "arm926ejs command group",
+		.chain = arm926ejs_exec_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
 /** Registers commands to access coprocessor, cache, and debug resources.  */
 int arm926ejs_register_commands(struct command_context *cmd_ctx)
 {
-	int retval;
-	struct command *arm926ejs_cmd;
-
-	retval = arm9tdmi_register_commands(cmd_ctx);
-
-	arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs",
-		NULL, COMMAND_ANY,
-		"arm926ejs specific commands");
-
-	register_command(cmd_ctx, arm926ejs_cmd, "cp15",
-		arm926ejs_handle_cp15_command, COMMAND_EXEC,
-		"display/modify cp15 register "
-		"<opcode_1> <opcode_2> <CRn> <CRm> [value]");
-
-	register_command(cmd_ctx, arm926ejs_cmd, "cache_info",
-		arm926ejs_handle_cache_info_command, COMMAND_EXEC,
-		"display information about target caches");
-
-	return retval;
+	arm9tdmi_register_commands(cmd_ctx);
+	return register_commands(cmd_ctx, NULL, arm926ejs_command_handlers);
 }
 
 /** Holds methods for ARM926 targets. */