X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=e0b1c70ae2d61d44e7b0a55af876082787427de8;hb=465a06dfdc6c5d4af377dac7b9d71845cb0dc034;hp=ca7728b01781ed8aa00c8bc7abe19fb723a99862;hpb=d0809ac060b35a04e7f0bceb96e1868663bd18df;p=openocd.git diff --git a/src/target/arm920t.c b/src/target/arm920t.c index ca7728b017..e0b1c70ae2 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -22,8 +22,10 @@ #endif #include "arm920t.h" -#include "time_support.h" +#include #include "target_type.h" +#include "register.h" +#include "arm_opcodes.h" /* @@ -51,17 +53,17 @@ #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z)) -static int arm920t_read_cp15_physical(target_t *target, +static int arm920t_read_cp15_physical(struct target *target, int reg_addr, uint32_t *value) { - struct arm920t_common_s *arm920t = target_to_arm920(target); - arm_jtag_t *jtag_info; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm_jtag *jtag_info; struct scan_field fields[4]; uint8_t access_type_buf = 1; uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 0; - jtag_info = &arm920t->arm9tdmi_common.arm7_9_common.jtag_info; + jtag_info = &arm920t->arm7_9_common.jtag_info; jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); @@ -103,18 +105,18 @@ static int arm920t_read_cp15_physical(target_t *target, return ERROR_OK; } -static int arm920t_write_cp15_physical(target_t *target, +static int arm920t_write_cp15_physical(struct target *target, int reg_addr, uint32_t value) { - struct arm920t_common_s *arm920t = target_to_arm920(target); - arm_jtag_t *jtag_info; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm_jtag *jtag_info; struct scan_field fields[4]; uint8_t access_type_buf = 1; uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 1; uint8_t value_buf[4]; - jtag_info = &arm920t->arm9tdmi_common.arm7_9_common.jtag_info; + jtag_info = &arm920t->arm7_9_common.jtag_info; buf_set_u32(value_buf, 0, 32, value); @@ -151,19 +153,19 @@ static int arm920t_write_cp15_physical(target_t *target, return ERROR_OK; } -static int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, +static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, uint32_t arm_opcode) { int retval; - struct arm920t_common_s *arm920t = target_to_arm920(target); - arm_jtag_t *jtag_info; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm_jtag *jtag_info; struct scan_field fields[4]; uint8_t access_type_buf = 0; /* interpreted access */ uint8_t reg_addr_buf = 0x0; uint8_t nr_w_buf = 0; uint8_t cp15_opcode_buf[4]; - jtag_info = &arm920t->arm9tdmi_common.arm7_9_common.jtag_info; + jtag_info = &arm920t->arm7_9_common.jtag_info; jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); @@ -208,13 +210,14 @@ static int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, return ERROR_OK; } -static int arm920t_read_cp15_interpreted(target_t *target, +static int arm920t_read_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); uint32_t* regs_p[1]; uint32_t regs[2]; uint32_t cp15c15 = 0x0; + struct reg *r = armv4_5->core_cache->reg_list; /* load address into R1 */ regs[1] = address; @@ -243,22 +246,23 @@ static int arm920t_read_cp15_interpreted(target_t *target, LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value); #endif - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; + r[0].dirty = 1; + r[1].dirty = 1; return ERROR_OK; } static -int arm920t_write_cp15_interpreted(target_t *target, +int arm920t_write_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t value, uint32_t address) { uint32_t cp15c15 = 0x0; - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); uint32_t regs[2]; + struct reg *r = armv4_5->core_cache->reg_list; /* load value, address into R0, R1 */ regs[0] = value; @@ -283,17 +287,17 @@ int arm920t_write_cp15_interpreted(target_t *target, LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address); #endif - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; + r[0].dirty = 1; + r[1].dirty = 1; return ERROR_OK; } // EXPORTED to FA256 -uint32_t arm920t_get_ttb(target_t *target) +uint32_t arm920t_get_ttb(struct target *target) { int retval; uint32_t ttb = 0x0; @@ -305,7 +309,7 @@ uint32_t arm920t_get_ttb(target_t *target) } // EXPORTED to FA256 -void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; @@ -326,7 +330,7 @@ void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ } // EXPORTED to FA256 -void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; @@ -347,10 +351,10 @@ void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c } // EXPORTED to FA256 -void arm920t_post_debug_entry(target_t *target) +void arm920t_post_debug_entry(struct target *target) { uint32_t cp15c15; - struct arm920t_common_s *arm920t = target_to_arm920(target); + struct arm920t_common *arm920t = target_to_arm920(target); /* examine cp15 control reg */ arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg); @@ -391,10 +395,10 @@ void arm920t_post_debug_entry(target_t *target) } // EXPORTED to FA256 -void arm920t_pre_restore_context(target_t *target) +void arm920t_pre_restore_context(struct target *target) { uint32_t cp15c15; - struct arm920t_common_s *arm920t = target_to_arm920(target); + struct arm920t_common *arm920t = target_to_arm920(target); /* restore i/d fault status and address register */ arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0); @@ -415,8 +419,8 @@ void arm920t_pre_restore_context(target_t *target) static const char arm920_not[] = "target is not an ARM920"; -static int arm920t_verify_pointer(struct command_context_s *cmd_ctx, - struct arm920t_common_s *arm920t) +static int arm920t_verify_pointer(struct command_context *cmd_ctx, + struct arm920t_common *arm920t) { if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { command_print(cmd_ctx, arm920_not); @@ -427,15 +431,15 @@ static int arm920t_verify_pointer(struct command_context_s *cmd_ctx, } /** Logs summary of ARM920 state for a halted target. */ -int arm920t_arch_state(struct target_s *target) +int arm920t_arch_state(struct target *target) { static const char *state[] = { "disabled", "enabled" }; - struct arm920t_common_s *arm920t = target_to_arm920(target); - struct armv4_5_common_s *armv4_5; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm *armv4_5; if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { @@ -443,16 +447,10 @@ int arm920t_arch_state(struct target_s *target) return ERROR_TARGET_INVALID; } - armv4_5 = &arm920t->arm9tdmi_common.arm7_9_common.armv4_5_common; + armv4_5 = &arm920t->arm7_9_common.armv4_5_common; - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, D-Cache: %s, I-Cache: %s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + arm_arch_state(target); + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", state[arm920t->armv4_5_mmu.mmu_enabled], state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); @@ -460,7 +458,7 @@ int arm920t_arch_state(struct target_s *target) return ERROR_OK; } -static int arm920_mmu(struct target_s *target, int *enabled) +static int arm920_mmu(struct target *target, int *enabled) { if (target->state != TARGET_HALTED) { LOG_ERROR("%s: target not halted", __func__); @@ -471,7 +469,7 @@ static int arm920_mmu(struct target_s *target, int *enabled) return ERROR_OK; } -static int arm920_virt2phys(struct target_s *target, +static int arm920_virt2phys(struct target *target, uint32_t virt, uint32_t *phys) { /** @todo Implement this! */ @@ -480,7 +478,7 @@ static int arm920_virt2phys(struct target_s *target, } /** Reads a buffer, in the specified word size, with current MMU settings. */ -int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -490,21 +488,21 @@ int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size } -static int arm920t_read_phys_memory(struct target_s *target, +static int arm920t_read_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - struct arm920t_common_s *arm920t = target_to_arm920(target); + struct arm920t_common *arm920t = target_to_arm920(target); return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer); } -static int arm920t_write_phys_memory(struct target_s *target, +static int arm920t_write_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - struct arm920t_common_s *arm920t = target_to_arm920(target); + struct arm920t_common *arm920t = target_to_arm920(target); return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer); @@ -512,7 +510,7 @@ static int arm920t_write_phys_memory(struct target_s *target, /** Writes a buffer, in the specified word size, with current MMU settings. */ -int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -525,7 +523,7 @@ int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t siz */ if (((size == 4) || (size == 2)) && (count == 1)) { - struct arm920t_common_s *arm920t = target_to_arm920(target); + struct arm920t_common *arm920t = target_to_arm920(target); if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { @@ -549,13 +547,13 @@ int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t siz } // EXPORTED to FA256 -int arm920t_soft_reset_halt(struct target_s *target) +int arm920t_soft_reset_halt(struct target *target) { int retval = ERROR_OK; - struct arm920t_common_s *arm920t = target_to_arm920(target); - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; if ((retval = target_halt(target)) != ERROR_OK) { @@ -595,18 +593,19 @@ int arm920t_soft_reset_halt(struct target_s *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; + + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); + armv4_5->cpsr->dirty = 1; /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; - arm920t_disable_mmu_caches(target, 1, 1, 1); arm920t->armv4_5_mmu.mmu_enabled = 0; arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; @@ -620,14 +619,25 @@ int arm920t_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, struct jtag_tap *tap) +/* FIXME remove forward decls */ +static int arm920t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); +static int arm920t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + +int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap) { - arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common; - arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; + struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common; - /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) - */ - arm9tdmi_init_arch_info(target, arm9tdmi, tap); + arm7_9->armv4_5_common.mrc = arm920t_mrc; + arm7_9->armv4_5_common.mcr = arm920t_mcr; + + /* initialize arm7/arm9 specific info (including armv4_5) */ + arm9tdmi_init_arch_info(target, arm7_9, tap); arm920t->common_magic = ARM920T_COMMON_MAGIC; @@ -655,9 +665,9 @@ int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, struct j return ERROR_OK; } -static int arm920t_target_create(struct target_s *target, Jim_Interp *interp) +static int arm920t_target_create(struct target *target, Jim_Interp *interp) { - arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t)); + struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common)); return arm920t_init_arch_info(target, arm920t, target->tap); } @@ -665,10 +675,10 @@ static int arm920t_target_create(struct target_s *target, Jim_Interp *interp) COMMAND_HANDLER(arm920t_handle_read_cache_command) { int retval = ERROR_OK; - target_t *target = get_current_target(cmd_ctx); - struct arm920t_common_s *arm920t = target_to_arm920(target); - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct target *target = get_current_target(CMD_CTX); + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm *armv4_5 = &arm7_9->armv4_5_common; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -676,20 +686,21 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) uint32_t C15_C_D_Ind, C15_C_I_Ind; int i; FILE *output; - arm920t_cache_line_t d_cache[8][64], i_cache[8][64]; + struct arm920t_cache_line d_cache[8][64], i_cache[8][64]; int segment, index; + struct reg *r; - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; - if (argc != 1) + if (CMD_ARGC != 1) { - command_print(cmd_ctx, "usage: arm920t read_cache "); + command_print(CMD_CTX, "usage: arm920t read_cache "); return ERROR_OK; } - if ((output = fopen(args[0], "w")) == NULL) + if ((output = fopen(CMD_ARGV[0], "w")) == NULL) { LOG_DEBUG("error opening cache content file"); return ERROR_OK; @@ -886,24 +897,29 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* restore CP15 MMU and Cache settings */ arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved); - command_print(cmd_ctx, "cache content successfully output to %s", args[0]); + command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]); fclose(output); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - /* mark registers dirty. */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; + /* force writeback of the valid data */ + r = armv4_5->core_cache->reg_list; + r[0].dirty = r[0].valid; + r[1].dirty = r[1].valid; + r[2].dirty = r[2].valid; + r[3].dirty = r[3].valid; + r[4].dirty = r[4].valid; + r[5].dirty = r[5].valid; + r[6].dirty = r[6].valid; + r[7].dirty = r[7].valid; + + r = arm_reg_current(armv4_5, 8); + r->dirty = r->valid; + + r = arm_reg_current(armv4_5, 9); + r->dirty = r->valid; return ERROR_OK; } @@ -911,10 +927,10 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) COMMAND_HANDLER(arm920t_handle_read_mmu_command) { int retval = ERROR_OK; - target_t *target = get_current_target(cmd_ctx); - struct arm920t_common_s *arm920t = target_to_arm920(target); - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct target *target = get_current_target(CMD_CTX); + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm *armv4_5 = &arm7_9->armv4_5_common; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -922,20 +938,21 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) int i; FILE *output; uint32_t Dlockdown, Ilockdown; - arm920t_tlb_entry_t d_tlb[64], i_tlb[64]; + struct arm920t_tlb_entry d_tlb[64], i_tlb[64]; int victim; + struct reg *r; - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; - if (argc != 1) + if (CMD_ARGC != 1) { - command_print(cmd_ctx, "usage: arm920t read_mmu "); + command_print(CMD_CTX, "usage: arm920t read_mmu "); return ERROR_OK; } - if ((output = fopen(args[0], "w")) == NULL) + if ((output = fopen(CMD_ARGV[0], "w")) == NULL) { LOG_DEBUG("error opening mmu content file"); return ERROR_OK; @@ -1169,24 +1186,29 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)"); } - command_print(cmd_ctx, "mmu content successfully output to %s", args[0]); + command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]); fclose(output); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - /* mark registers dirty */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; + /* force writeback of the valid data */ + r = armv4_5->core_cache->reg_list; + r[0].dirty = r[0].valid; + r[1].dirty = r[1].valid; + r[2].dirty = r[2].valid; + r[3].dirty = r[3].valid; + r[4].dirty = r[4].valid; + r[5].dirty = r[5].valid; + r[6].dirty = r[6].valid; + r[7].dirty = r[7].valid; + + r = arm_reg_current(armv4_5, 8); + r->dirty = r->valid; + + r = arm_reg_current(armv4_5, 9); + r->dirty = r->valid; return ERROR_OK; } @@ -1194,31 +1216,31 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) COMMAND_HANDLER(arm920t_handle_cp15_command) { int retval; - target_t *target = get_current_target(cmd_ctx); - struct arm920t_common_s *arm920t = target_to_arm920(target); + struct target *target = get_current_target(CMD_CTX); + struct arm920t_common *arm920t = target_to_arm920(target); - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (argc >= 1) + if (CMD_ARGC >= 1) { int address; - COMMAND_PARSE_NUMBER(int, args[0], address); + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address); - if (argc == 1) + if (CMD_ARGC == 1) { uint32_t value; if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access reg %i", address); + command_print(CMD_CTX, "couldn't access reg %i", address); return ERROR_OK; } if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -1226,18 +1248,18 @@ COMMAND_HANDLER(arm920t_handle_cp15_command) return retval; } - command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value); + command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value); } - else if (argc == 2) + else if (CMD_ARGC == 2) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access reg %i", address); + command_print(CMD_CTX, "couldn't access reg %i", address); return ERROR_OK; } - command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value); + command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value); } } @@ -1247,65 +1269,65 @@ COMMAND_HANDLER(arm920t_handle_cp15_command) COMMAND_HANDLER(arm920t_handle_cp15i_command) { int retval; - target_t *target = get_current_target(cmd_ctx); - struct arm920t_common_s *arm920t = target_to_arm920(target); + struct target *target = get_current_target(CMD_CTX); + struct arm920t_common *arm920t = target_to_arm920(target); - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (argc >= 1) + if (CMD_ARGC >= 1) { uint32_t opcode; - COMMAND_PARSE_NUMBER(u32, args[0], opcode); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode); - if (argc == 1) + if (CMD_ARGC == 1) { uint32_t value; if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); } - else if (argc == 2) + else if (CMD_ARGC == 2) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); } - else if (argc == 3) + else if (CMD_ARGC == 3) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); uint32_t address; - COMMAND_PARSE_NUMBER(u32, args[2], address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address); if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address); } } else { - command_print(cmd_ctx, "usage: arm920t cp15i [value] [address]"); + command_print(CMD_CTX, "usage: arm920t cp15i [value] [address]"); } return ERROR_OK; @@ -1314,18 +1336,21 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command) COMMAND_HANDLER(arm920t_handle_cache_info_command) { int retval; - target_t *target = get_current_target(cmd_ctx); - struct arm920t_common_s *arm920t = target_to_arm920(target); + struct target *target = get_current_target(CMD_CTX); + struct arm920t_common *arm920t = target_to_arm920(target); - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; - return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache); + return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache); } -static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int arm920t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value) { if (cpnum!=15) { @@ -1333,10 +1358,16 @@ static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, return ERROR_FAIL; } - return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value); + /* read "to" r0 */ + return arm920t_read_cp15_interpreted(target, + ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + 0, value); } -static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int arm920t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value) { if (cpnum!=15) { @@ -1344,43 +1375,66 @@ static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, return ERROR_FAIL; } - return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value); + /* write "from" r0 */ + return arm920t_write_cp15_interpreted(target, + ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + 0, value); } -/** Registers commands to access coprocessor, cache, and MMU resources. */ -int arm920t_register_commands(struct command_context_s *cmd_ctx) -{ - int retval; - command_t *arm920t_cmd; - - retval = arm9tdmi_register_commands(cmd_ctx); - - arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", - NULL, COMMAND_ANY, - "arm920t specific commands"); - - register_command(cmd_ctx, arm920t_cmd, "cp15", - arm920t_handle_cp15_command, COMMAND_EXEC, - "display/modify cp15 register [value]"); - register_command(cmd_ctx, arm920t_cmd, "cp15i", - arm920t_handle_cp15i_command, COMMAND_EXEC, - "display/modify cp15 (interpreted access) " - " [value] [address]"); - register_command(cmd_ctx, arm920t_cmd, "cache_info", - arm920t_handle_cache_info_command, COMMAND_EXEC, - "display information about target caches"); - register_command(cmd_ctx, arm920t_cmd, "read_cache", - arm920t_handle_read_cache_command, COMMAND_EXEC, - "display I/D cache content"); - register_command(cmd_ctx, arm920t_cmd, "read_mmu", - arm920t_handle_read_mmu_command, COMMAND_EXEC, - "display I/D mmu content"); - - return retval; -} +static const struct command_registration arm920t_exec_command_handlers[] = { + { + .name = "cp15", + .handler = arm920t_handle_cp15_command, + .mode = COMMAND_EXEC, + .help = "display/modify cp15 register", + .usage = "regnum [value]", + }, + { + .name = "cp15i", + .handler = arm920t_handle_cp15i_command, + .mode = COMMAND_EXEC, + /* prefer using less error-prone "arm mcr" or "arm mrc" */ + .help = "display/modify cp15 register using ARM opcode" + " (DEPRECATED)", + .usage = "instruction [value [address]]", + }, + { + .name = "cache_info", + .handler = arm920t_handle_cache_info_command, + .mode = COMMAND_EXEC, + .help = "display information about target caches", + }, + { + .name = "read_cache", + .handler = arm920t_handle_read_cache_command, + .mode = COMMAND_EXEC, + .help = "dump I/D cache content to file", + .usage = "filename", + }, + { + .name = "read_mmu", + .handler = arm920t_handle_read_mmu_command, + .mode = COMMAND_EXEC, + .help = "dump I/D mmu content to file", + .usage = "filename", + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration arm920t_command_handlers[] = { + { + .chain = arm9tdmi_command_handlers, + }, + { + .name = "arm920t", + .mode = COMMAND_ANY, + .help = "arm920t command group", + .chain = arm920t_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; /** Holds methods for ARM920 targets. */ -target_type_t arm920t_target = +struct target_type arm920t_target = { .name = "arm920t", @@ -1397,7 +1451,7 @@ target_type_t arm920t_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm920t_soft_reset_halt, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm920t_read_memory, .write_memory = arm920t_write_memory, @@ -1407,8 +1461,9 @@ target_type_t arm920t_target = .virt2phys = arm920_virt2phys, .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -1417,10 +1472,9 @@ target_type_t arm920t_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm920t_register_commands, + .commands = arm920t_command_handlers, .target_create = arm920t_target_create, .init_target = arm9tdmi_init_target, - .examine = arm9tdmi_examine, - .mrc = arm920t_mrc, - .mcr = arm920t_mcr, + .examine = arm7_9_examine, + .check_reset = arm7_9_check_reset, };