X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=e0b1c70ae2d61d44e7b0a55af876082787427de8;hb=465a06dfdc6c5d4af377dac7b9d71845cb0dc034;hp=9cd491f3ea2df09ca68ff7083da2264f89f6edc6;hpb=5706fd7860ea01c591ecf74880a5a5e04e6df22e;p=openocd.git diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 9cd491f3ea..e0b1c70ae2 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -22,9 +22,10 @@ #endif #include "arm920t.h" -#include "time_support.h" +#include #include "target_type.h" #include "register.h" +#include "arm_opcodes.h" /* @@ -212,10 +213,11 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, static int arm920t_read_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); uint32_t* regs_p[1]; uint32_t regs[2]; uint32_t cp15c15 = 0x0; + struct reg *r = armv4_5->core_cache->reg_list; /* load address into R1 */ regs[1] = address; @@ -247,8 +249,8 @@ static int arm920t_read_cp15_interpreted(struct target *target, if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; + r[0].dirty = 1; + r[1].dirty = 1; return ERROR_OK; } @@ -258,8 +260,9 @@ int arm920t_write_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t value, uint32_t address) { uint32_t cp15c15 = 0x0; - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); uint32_t regs[2]; + struct reg *r = armv4_5->core_cache->reg_list; /* load value, address into R0, R1 */ regs[0] = value; @@ -287,8 +290,8 @@ int arm920t_write_cp15_interpreted(struct target *target, if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; + r[0].dirty = 1; + r[1].dirty = 1; return ERROR_OK; } @@ -436,7 +439,7 @@ int arm920t_arch_state(struct target *target) }; struct arm920t_common *arm920t = target_to_arm920(target); - struct armv4_5_common_s *armv4_5; + struct arm *armv4_5; if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { @@ -446,14 +449,8 @@ int arm920t_arch_state(struct target *target) armv4_5 = &arm920t->arm7_9_common.armv4_5_common; - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, D-Cache: %s, I-Cache: %s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, - arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->cpsr->value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + arm_arch_state(target); + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", state[arm920t->armv4_5_mmu.mmu_enabled], state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); @@ -555,7 +552,7 @@ int arm920t_soft_reset_halt(struct target *target) int retval = ERROR_OK; struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct arm *armv4_5 = &arm7_9->armv4_5_common; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; if ((retval = target_halt(target)) != ERROR_OK) @@ -596,18 +593,19 @@ int arm920t_soft_reset_halt(struct target *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->cpsr->value, 0, 8, 0xd3); + uint32_t cpsr; + + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); armv4_5->cpsr->dirty = 1; - armv4_5->cpsr->valid = 1; /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; - arm920t_disable_mmu_caches(target, 1, 1, 1); arm920t->armv4_5_mmu.mmu_enabled = 0; arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; @@ -621,10 +619,23 @@ int arm920t_soft_reset_halt(struct target *target) return ERROR_OK; } +/* FIXME remove forward decls */ +static int arm920t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); +static int arm920t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap) { struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common; + arm7_9->armv4_5_common.mrc = arm920t_mrc; + arm7_9->armv4_5_common.mcr = arm920t_mcr; + /* initialize arm7/arm9 specific info (including armv4_5) */ arm9tdmi_init_arch_info(target, arm7_9, tap); @@ -667,7 +678,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct arm *armv4_5 = &arm7_9->armv4_5_common; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -677,6 +688,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) FILE *output; struct arm920t_cache_line d_cache[8][64], i_cache[8][64]; int segment, index; + struct reg *r; retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) @@ -892,17 +904,22 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - /* mark registers dirty. */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; + /* force writeback of the valid data */ + r = armv4_5->core_cache->reg_list; + r[0].dirty = r[0].valid; + r[1].dirty = r[1].valid; + r[2].dirty = r[2].valid; + r[3].dirty = r[3].valid; + r[4].dirty = r[4].valid; + r[5].dirty = r[5].valid; + r[6].dirty = r[6].valid; + r[7].dirty = r[7].valid; + + r = arm_reg_current(armv4_5, 8); + r->dirty = r->valid; + + r = arm_reg_current(armv4_5, 9); + r->dirty = r->valid; return ERROR_OK; } @@ -913,7 +930,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct arm *armv4_5 = &arm7_9->armv4_5_common; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -923,6 +940,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) uint32_t Dlockdown, Ilockdown; struct arm920t_tlb_entry d_tlb[64], i_tlb[64]; int victim; + struct reg *r; retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) @@ -1175,17 +1193,22 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - /* mark registers dirty */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; + /* force writeback of the valid data */ + r = armv4_5->core_cache->reg_list; + r[0].dirty = r[0].valid; + r[1].dirty = r[1].valid; + r[2].dirty = r[2].valid; + r[3].dirty = r[3].valid; + r[4].dirty = r[4].valid; + r[5].dirty = r[5].valid; + r[6].dirty = r[6].valid; + r[7].dirty = r[7].valid; + + r = arm_reg_current(armv4_5, 8); + r->dirty = r->valid; + + r = arm_reg_current(armv4_5, 9); + r->dirty = r->valid; return ERROR_OK; } @@ -1324,7 +1347,10 @@ COMMAND_HANDLER(arm920t_handle_cache_info_command) } -static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int arm920t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value) { if (cpnum!=15) { @@ -1332,10 +1358,16 @@ static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t return ERROR_FAIL; } - return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value); + /* read "to" r0 */ + return arm920t_read_cp15_interpreted(target, + ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + 0, value); } -static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int arm920t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value) { if (cpnum!=15) { @@ -1343,40 +1375,63 @@ static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t return ERROR_FAIL; } - return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value); + /* write "from" r0 */ + return arm920t_write_cp15_interpreted(target, + ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + 0, value); } -/** Registers commands to access coprocessor, cache, and MMU resources. */ -int arm920t_register_commands(struct command_context *cmd_ctx) -{ - int retval; - struct command *arm920t_cmd; - - retval = arm9tdmi_register_commands(cmd_ctx); - - arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", - NULL, COMMAND_ANY, - "arm920t specific commands"); - - register_command(cmd_ctx, arm920t_cmd, "cp15", - arm920t_handle_cp15_command, COMMAND_EXEC, - "display/modify cp15 register [value]"); - register_command(cmd_ctx, arm920t_cmd, "cp15i", - arm920t_handle_cp15i_command, COMMAND_EXEC, - "display/modify cp15 (interpreted access) " - " [value] [address]"); - register_command(cmd_ctx, arm920t_cmd, "cache_info", - arm920t_handle_cache_info_command, COMMAND_EXEC, - "display information about target caches"); - register_command(cmd_ctx, arm920t_cmd, "read_cache", - arm920t_handle_read_cache_command, COMMAND_EXEC, - "display I/D cache content"); - register_command(cmd_ctx, arm920t_cmd, "read_mmu", - arm920t_handle_read_mmu_command, COMMAND_EXEC, - "display I/D mmu content"); - - return retval; -} +static const struct command_registration arm920t_exec_command_handlers[] = { + { + .name = "cp15", + .handler = arm920t_handle_cp15_command, + .mode = COMMAND_EXEC, + .help = "display/modify cp15 register", + .usage = "regnum [value]", + }, + { + .name = "cp15i", + .handler = arm920t_handle_cp15i_command, + .mode = COMMAND_EXEC, + /* prefer using less error-prone "arm mcr" or "arm mrc" */ + .help = "display/modify cp15 register using ARM opcode" + " (DEPRECATED)", + .usage = "instruction [value [address]]", + }, + { + .name = "cache_info", + .handler = arm920t_handle_cache_info_command, + .mode = COMMAND_EXEC, + .help = "display information about target caches", + }, + { + .name = "read_cache", + .handler = arm920t_handle_read_cache_command, + .mode = COMMAND_EXEC, + .help = "dump I/D cache content to file", + .usage = "filename", + }, + { + .name = "read_mmu", + .handler = arm920t_handle_read_mmu_command, + .mode = COMMAND_EXEC, + .help = "dump I/D mmu content to file", + .usage = "filename", + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration arm920t_command_handlers[] = { + { + .chain = arm9tdmi_command_handlers, + }, + { + .name = "arm920t", + .mode = COMMAND_ANY, + .help = "arm920t command group", + .chain = arm920t_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; /** Holds methods for ARM920 targets. */ struct target_type arm920t_target = @@ -1396,7 +1451,7 @@ struct target_type arm920t_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm920t_soft_reset_halt, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm920t_read_memory, .write_memory = arm920t_write_memory, @@ -1417,10 +1472,9 @@ struct target_type arm920t_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm920t_register_commands, + .commands = arm920t_command_handlers, .target_create = arm920t_target_create, .init_target = arm9tdmi_init_target, .examine = arm7_9_examine, - .mrc = arm920t_mrc, - .mcr = arm920t_mcr, + .check_reset = arm7_9_check_reset, };