X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=e0b1c70ae2d61d44e7b0a55af876082787427de8;hb=465a06dfdc6c5d4af377dac7b9d71845cb0dc034;hp=1e6019cb1c4ff49ca4c7cb604572d9f5df60d7f5;hpb=509fe82b07df4a7e6217bfde37374e90262aa2de;p=openocd.git diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 1e6019cb1c..e0b1c70ae2 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -22,9 +22,10 @@ #endif #include "arm920t.h" -#include "time_support.h" +#include #include "target_type.h" #include "register.h" +#include "arm_opcodes.h" /* @@ -212,7 +213,7 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, static int arm920t_read_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value) { - struct arm *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); uint32_t* regs_p[1]; uint32_t regs[2]; uint32_t cp15c15 = 0x0; @@ -259,7 +260,7 @@ int arm920t_write_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t value, uint32_t address) { uint32_t cp15c15 = 0x0; - struct arm *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); uint32_t regs[2]; struct reg *r = armv4_5->core_cache->reg_list; @@ -448,14 +449,8 @@ int arm920t_arch_state(struct target *target) armv4_5 = &arm920t->arm7_9_common.armv4_5_common; - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, D-Cache: %s, I-Cache: %s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, - arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->cpsr->value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + arm_arch_state(target); + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", state[arm920t->armv4_5_mmu.mmu_enabled], state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); @@ -624,10 +619,23 @@ int arm920t_soft_reset_halt(struct target *target) return ERROR_OK; } +/* FIXME remove forward decls */ +static int arm920t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); +static int arm920t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap) { struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common; + arm7_9->armv4_5_common.mrc = arm920t_mrc; + arm7_9->armv4_5_common.mcr = arm920t_mcr; + /* initialize arm7/arm9 specific info (including armv4_5) */ arm9tdmi_init_arch_info(target, arm7_9, tap); @@ -1339,7 +1347,10 @@ COMMAND_HANDLER(arm920t_handle_cache_info_command) } -static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int arm920t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value) { if (cpnum!=15) { @@ -1347,10 +1358,16 @@ static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t return ERROR_FAIL; } - return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value); + /* read "to" r0 */ + return arm920t_read_cp15_interpreted(target, + ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + 0, value); } -static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int arm920t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value) { if (cpnum!=15) { @@ -1358,45 +1375,55 @@ static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t return ERROR_FAIL; } - return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value); + /* write "from" r0 */ + return arm920t_write_cp15_interpreted(target, + ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + 0, value); } static const struct command_registration arm920t_exec_command_handlers[] = { { .name = "cp15", - .handler = &arm920t_handle_cp15_command, + .handler = arm920t_handle_cp15_command, .mode = COMMAND_EXEC, .help = "display/modify cp15 register", - .usage = " [value]", + .usage = "regnum [value]", }, { .name = "cp15i", - .handler = &arm920t_handle_cp15i_command, + .handler = arm920t_handle_cp15i_command, .mode = COMMAND_EXEC, - .help = "display/modify cp15 (interpreted access)", - .usage = " [value] [address]", + /* prefer using less error-prone "arm mcr" or "arm mrc" */ + .help = "display/modify cp15 register using ARM opcode" + " (DEPRECATED)", + .usage = "instruction [value [address]]", }, { .name = "cache_info", - .handler = &arm920t_handle_cache_info_command, + .handler = arm920t_handle_cache_info_command, .mode = COMMAND_EXEC, .help = "display information about target caches", }, { .name = "read_cache", - .handler = &arm920t_handle_read_cache_command, + .handler = arm920t_handle_read_cache_command, .mode = COMMAND_EXEC, - .help = "display I/D cache content", + .help = "dump I/D cache content to file", + .usage = "filename", }, { .name = "read_mmu", - .handler = &arm920t_handle_read_mmu_command, + .handler = arm920t_handle_read_mmu_command, .mode = COMMAND_EXEC, - .help = "display I/D mmu content", + .help = "dump I/D mmu content to file", + .usage = "filename", }, COMMAND_REGISTRATION_DONE }; -static const struct command_registration arm920t_command_handlers[] = { +const struct command_registration arm920t_command_handlers[] = { + { + .chain = arm9tdmi_command_handlers, + }, { .name = "arm920t", .mode = COMMAND_ANY, @@ -1406,13 +1433,6 @@ static const struct command_registration arm920t_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -/** Registers commands to access coprocessor, cache, and MMU resources. */ -int arm920t_register_commands(struct command_context *cmd_ctx) -{ - arm9tdmi_register_commands(cmd_ctx); - return register_commands(cmd_ctx, NULL, arm920t_command_handlers); -} - /** Holds methods for ARM920 targets. */ struct target_type arm920t_target = { @@ -1431,7 +1451,7 @@ struct target_type arm920t_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm920t_soft_reset_halt, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm920t_read_memory, .write_memory = arm920t_write_memory, @@ -1452,10 +1472,9 @@ struct target_type arm920t_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm920t_register_commands, + .commands = arm920t_command_handlers, .target_create = arm920t_target_create, .init_target = arm9tdmi_init_target, .examine = arm7_9_examine, - .mrc = arm920t_mrc, - .mcr = arm920t_mcr, + .check_reset = arm7_9_check_reset, };