X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=6e4e076ffa9ceb2f395a371447fccaf38296551e;hb=db7e77237c5a8104b527aeb23a2546b4bab92d8a;hp=f07cee8d9d1a42b551fe6241c329ec2c10e91c1e;hpb=4d88c124b1262a738b4a9f107ef62404a45bf323;p=openocd.git diff --git a/src/target/arm920t.c b/src/target/arm920t.c index f07cee8d9d..6e4e076ffa 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -22,12 +22,9 @@ #endif #include "arm920t.h" -#include "jtag.h" -#include "log.h" #include "time_support.h" +#include "target_type.h" -#include -#include #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ @@ -51,8 +48,8 @@ int arm920t_target_create(struct target_s *target, Jim_Interp *interp); int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm920t_quit(void); int arm920t_arch_state(struct target_s *target); -int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); -int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); +int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); +int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); int arm920t_soft_reset_halt(struct target_s *target); #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z)) @@ -96,68 +93,49 @@ target_type_t arm920t_target = .quit = arm920t_quit }; -int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value) +int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; scan_field_t fields[4]; - u8 access_type_buf = 1; - u8 reg_addr_buf = reg_addr & 0x3f; - u8 nr_w_buf = 0; + uint8_t access_type_buf = 1; + uint8_t reg_addr_buf = reg_addr & 0x3f; + uint8_t nr_w_buf = 0; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; - fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; - fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 6; fields[2].out_value = ®_addr_buf; - fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; - fields[3].in_value = NULL; - fields[3].in_check_value = NULL; - fields[3].in_check_mask = NULL; - fields[3].in_handler = NULL; - fields[3].in_handler_priv = NULL; - jtag_add_dr_scan(4, fields, TAP_INVALID); + jtag_add_dr_scan(4, fields, jtag_get_end_state()); - fields[1].in_handler_priv = value; - fields[1].in_handler = arm_jtag_buf_to_u32; /* deprecated! invoke this from user code! */ + fields[1].in_value = (uint8_t *)value; - jtag_add_dr_scan(4, fields, TAP_INVALID); + jtag_add_dr_scan(4, fields, jtag_get_end_state()); -#ifdef _DEBUG_INSTRUCTION_EXECUTION_ + jtag_add_callback(arm_le_to_h_u32, (uint8_t *)value); + + #ifdef _DEBUG_INSTRUCTION_EXECUTION_ jtag_execute_queue(); LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value); #endif @@ -165,64 +143,44 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value) return ERROR_OK; } -int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) +int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; scan_field_t fields[4]; - u8 access_type_buf = 1; - u8 reg_addr_buf = reg_addr & 0x3f; - u8 nr_w_buf = 1; - u8 value_buf[4]; + uint8_t access_type_buf = 1; + uint8_t reg_addr_buf = reg_addr & 0x3f; + uint8_t nr_w_buf = 1; + uint8_t value_buf[4]; buf_set_u32(value_buf, 0, 32, value); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; - fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = value_buf; - fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 6; fields[2].out_value = ®_addr_buf; - fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; - fields[3].in_value = NULL; - fields[3].in_check_value = NULL; - fields[3].in_check_mask = NULL; - fields[3].in_handler = NULL; - fields[3].in_handler_priv = NULL; - jtag_add_dr_scan(4, fields, TAP_INVALID); + jtag_add_dr_scan(4, fields, jtag_get_end_state()); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value); @@ -231,19 +189,19 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) return ERROR_OK; } -int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) +int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; scan_field_t fields[4]; - u8 access_type_buf = 0; /* interpreted access */ - u8 reg_addr_buf = 0x0; - u8 nr_w_buf = 0; - u8 cp15_opcode_buf[4]; + uint8_t access_type_buf = 0; /* interpreted access */ + uint8_t reg_addr_buf = 0x0; + uint8_t nr_w_buf = 0; + uint8_t cp15_opcode_buf[4]; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -252,44 +210,24 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; - fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = cp15_opcode_buf; - fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 6; fields[2].out_value = ®_addr_buf; - fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; - fields[3].in_value = NULL; - fields[3].in_check_value = NULL; - fields[3].in_check_mask = NULL; - fields[3].in_handler = NULL; - fields[3].in_handler_priv = NULL; - jtag_add_dr_scan(4, fields, TAP_INVALID); + jtag_add_dr_scan(4, fields, jtag_get_end_state()); arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); @@ -306,12 +244,12 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) return ERROR_OK; } -int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value) +int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value) { armv4_5_common_t *armv4_5 = target->arch_info; - u32* regs_p[1]; - u32 regs[2]; - u32 cp15c15 = 0x0; + uint32_t* regs_p[1]; + uint32_t regs[2]; + uint32_t cp15c15 = 0x0; /* load address into R1 */ regs[1] = address; @@ -349,11 +287,11 @@ int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address return ERROR_OK; } -int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address) +int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address) { - u32 cp15c15 = 0x0; + uint32_t cp15c15 = 0x0; armv4_5_common_t *armv4_5 = target->arch_info; - u32 regs[2]; + uint32_t regs[2]; /* load value, address into R0, R1 */ regs[0] = value; @@ -387,10 +325,10 @@ int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, return ERROR_OK; } -u32 arm920t_get_ttb(target_t *target) +uint32_t arm920t_get_ttb(target_t *target) { int retval; - u32 ttb = 0x0; + uint32_t ttb = 0x0; if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK) return retval; @@ -400,7 +338,7 @@ u32 arm920t_get_ttb(target_t *target) void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) { - u32 cp15_control; + uint32_t cp15_control; /* read cp15 control register */ arm920t_read_cp15_physical(target, 0x2, &cp15_control); @@ -420,7 +358,7 @@ void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) { - u32 cp15_control; + uint32_t cp15_control; /* read cp15 control register */ arm920t_read_cp15_physical(target, 0x2, &cp15_control); @@ -440,7 +378,7 @@ void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c void arm920t_post_debug_entry(target_t *target) { - u32 cp15c15; + uint32_t cp15c15; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; @@ -453,7 +391,7 @@ void arm920t_post_debug_entry(target_t *target) if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1) { - u32 cache_type_reg; + uint32_t cache_type_reg; /* identify caches */ arm920t_read_cp15_physical(target, 0x1, &cache_type_reg); jtag_execute_queue(); @@ -486,7 +424,7 @@ void arm920t_post_debug_entry(target_t *target) void arm920t_pre_restore_context(target_t *target) { - u32 cp15c15; + uint32_t cp15c15; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; @@ -580,7 +518,7 @@ int arm920t_arch_state(struct target_s *target) return ERROR_OK; } -int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -589,7 +527,7 @@ int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 coun return retval; } -int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -605,7 +543,7 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { LOG_DEBUG("D-Cache enabled, writing through to main memory"); - u32 pa, cb, ap; + uint32_t pa, cb, ap; int type, domain; pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap); @@ -635,7 +573,7 @@ int arm920t_soft_reset_halt(struct target_s *target) arm920t_common_t *arm920t = arm9tdmi->arch_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - if((retval = target_halt(target)) != ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) { return retval; } @@ -647,7 +585,7 @@ int arm920t_soft_reset_halt(struct target_s *target) if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { embeddedice_read_reg(dbg_stat); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -690,7 +628,7 @@ int arm920t_soft_reset_halt(struct target_s *target) arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) { return retval; } @@ -793,11 +731,11 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c arm9tdmi_common_t *arm9tdmi; arm920t_common_t *arm920t; arm_jtag_t *jtag_info; - u32 cp15c15; - u32 cp15_ctrl, cp15_ctrl_saved; - u32 regs[16]; - u32 *regs_p[16]; - u32 C15_C_D_Ind, C15_C_I_Ind; + uint32_t cp15c15; + uint32_t cp15_ctrl, cp15_ctrl_saved; + uint32_t regs[16]; + uint32_t *regs_p[16]; + uint32_t C15_C_D_Ind, C15_C_I_Ind; int i; FILE *output; arm920t_cache_line_t d_cache[8][64], i_cache[8][64]; @@ -828,7 +766,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* disable MMU and Caches */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -891,7 +829,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* read D RAM and CAM content */ arm9tdmi_read_core_regs(target, 0x3fe, regs_p); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -977,7 +915,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* read I RAM and CAM content */ arm9tdmi_read_core_regs(target, 0x3fe, regs_p); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -1045,13 +983,13 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd arm9tdmi_common_t *arm9tdmi; arm920t_common_t *arm920t; arm_jtag_t *jtag_info; - u32 cp15c15; - u32 cp15_ctrl, cp15_ctrl_saved; - u32 regs[16]; - u32 *regs_p[16]; + uint32_t cp15c15; + uint32_t cp15_ctrl, cp15_ctrl_saved; + uint32_t regs[16]; + uint32_t *regs_p[16]; int i; FILE *output; - u32 Dlockdown, Ilockdown; + uint32_t Dlockdown, Ilockdown; arm920t_tlb_entry_t d_tlb[64], i_tlb[64]; int victim; @@ -1080,7 +1018,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* disable MMU and Caches */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -1090,7 +1028,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read CP15 test state register */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -1111,7 +1049,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read D TLB lockdown stored to r1 */ arm9tdmi_read_core_regs(target, 0x2, regs_p); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -1140,7 +1078,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read D TLB CAM content stored to r2-r9 */ arm9tdmi_read_core_regs(target, 0x3fc, regs_p); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -1175,7 +1113,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read D TLB RAM content stored to r2 and r3 */ arm9tdmi_read_core_regs(target, 0xc, regs_p); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -1207,7 +1145,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read I TLB lockdown stored to r1 */ arm9tdmi_read_core_regs(target, 0x2, regs_p); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -1236,7 +1174,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read I TLB CAM content stored to r2-r9 */ arm9tdmi_read_core_regs(target, 0x3fc, regs_p); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -1271,7 +1209,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read I TLB RAM content stored to r2 and r3 */ arm9tdmi_read_core_regs(target, 0xc, regs_p); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -1355,13 +1293,13 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch if (argc == 1) { - u32 value; + uint32_t value; if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK) { command_print(cmd_ctx, "couldn't access reg %i", address); return ERROR_OK; } - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -1370,7 +1308,7 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch } else if (argc == 2) { - u32 value = strtoul(args[1], NULL, 0); + uint32_t value = strtoul(args[1], NULL, 0); if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK) { command_print(cmd_ctx, "couldn't access reg %i", address); @@ -1410,11 +1348,11 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c /* one or more argument, access a single register (write if second argument is given */ if (argc >= 1) { - u32 opcode = strtoul(args[0], NULL, 0); + uint32_t opcode = strtoul(args[0], NULL, 0); if (argc == 1) { - u32 value; + uint32_t value; if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK) { command_print(cmd_ctx, "couldn't execute %8.8x", opcode); @@ -1425,7 +1363,7 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c } else if (argc == 2) { - u32 value = strtoul(args[1], NULL, 0); + uint32_t value = strtoul(args[1], NULL, 0); if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK) { command_print(cmd_ctx, "couldn't execute %8.8x", opcode); @@ -1435,8 +1373,8 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c } else if (argc == 3) { - u32 value = strtoul(args[1], NULL, 0); - u32 address = strtoul(args[2], NULL, 0); + uint32_t value = strtoul(args[1], NULL, 0); + uint32_t address = strtoul(args[2], NULL, 0); if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK) { command_print(cmd_ctx, "couldn't execute %8.8x", opcode);