X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=dab16cfcdb536c1de66df8265fcae80c69d22f52;hb=8d73c2a9b0c00c870694a57f7cfbc23e354855ac;hp=0531cad6cdd7eb7e6cf9a9410316d2363cace709;hpb=db7c3810c2248c0560e00ab4f0532ffab2f173a7;p=openocd.git diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 0531cad6cd..dab16cfcdb 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -35,6 +35,7 @@ #include "log.h" #include "arm7_9_common.h" #include "breakpoints.h" +#include "time_support.h" #include #include @@ -53,53 +54,89 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm7_9_reinit_embeddedice(target_t *target) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - - breakpoint_t *breakpoint = target->breakpoints; - arm7_9->wp_available = 2; +static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) +{ + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); + arm7_9->sw_breakpoints_added = 0; arm7_9->wp0_used = 0; - arm7_9->wp1_used = 0; + arm7_9->wp1_used = arm7_9->wp1_used_default; + arm7_9->wp_available = arm7_9->wp_available_max; - /* mark all hardware breakpoints as unset */ - while (breakpoint) + return jtag_execute_queue(); +} + +/* set up embedded ice registers */ +static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) +{ + if (arm7_9->sw_breakpoints_added) { - if (breakpoint->type == BKPT_HARD) - { - breakpoint->set = 0; - } - breakpoint = breakpoint->next; + return ERROR_OK; + } + if (arm7_9->wp_available < 1) + { + LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + arm7_9->wp_available--; + + /* pick a breakpoint unit */ + if (!arm7_9->wp0_used) + { + arm7_9->sw_breakpoints_added=1; + arm7_9->wp0_used = 3; + } else if (!arm7_9->wp1_used) + { + arm7_9->sw_breakpoints_added=2; + arm7_9->wp1_used = 3; + } + else + { + LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); + return ERROR_FAIL; } - if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp) + if (arm7_9->sw_breakpoints_added==1) { - arm7_9->sw_bkpts_enabled = 0; - arm7_9_enable_sw_bkpts(target); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); + } + else if (arm7_9->sw_breakpoints_added==2) + { + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); + } + else + { + LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); + return ERROR_FAIL; } - return ERROR_OK; + return jtag_execute_queue(); } /* set things up after a reset / on startup */ int arm7_9_setup(target_t *target) { - /* a test-logic reset have occured - * the EmbeddedICE registers have been reset - * hardware breakpoints have been cleared - */ - return arm7_9_reinit_embeddedice(target); + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + + return arm7_9_clear_watchpoints(arm7_9); } + int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -121,10 +158,14 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm return ERROR_OK; } +/* we set up the breakpoint even if it is already set. Some action, e.g. reset + * might have erased the values in embedded ice + */ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; + int retval=ERROR_OK; if (target->state != TARGET_HALTED) { @@ -132,51 +173,43 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_TARGET_NOT_HALTED; } - if (arm7_9->force_hw_bkpts) - breakpoint->type = BKPT_HARD; - - if (breakpoint->set) - { - LOG_WARNING("breakpoint already set"); - return ERROR_OK; - } - if (breakpoint->type == BKPT_HARD) { /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */ u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u; - if (!arm7_9->wp0_used) + if (breakpoint->set==1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - - jtag_execute_queue(); - arm7_9->wp0_used = 1; - breakpoint->set = 1; } - else if (!arm7_9->wp1_used) + else if (breakpoint->set==2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - - jtag_execute_queue(); - arm7_9->wp1_used = 1; - breakpoint->set = 2; } else { LOG_ERROR("BUG: no hardware comparator available"); return ERROR_OK; } + + retval=jtag_execute_queue(); } else if (breakpoint->type == BKPT_SOFT) { + if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK) + return retval; + + /* did we already set this breakpoint? */ + if (breakpoint->set) + return ERROR_OK; + if (breakpoint->length == 4) { u32 verify = 0xffffffff; @@ -210,7 +243,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) breakpoint->set = 1; } - return ERROR_OK; + return retval; } @@ -219,12 +252,6 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); @@ -236,15 +263,14 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); - jtag_execute_queue(); arm7_9->wp0_used = 0; } else if (breakpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); - jtag_execute_queue(); arm7_9->wp1_used = 0; } + jtag_execute_queue(); breakpoint->set = 0; } else @@ -282,17 +308,13 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - - if (arm7_9->force_hw_bkpts) - { - LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address); - breakpoint->type = BKPT_HARD; - } - - if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0)) + + if (arm7_9->breakpoint_count==0) { - LOG_INFO("sw breakpoint requested, but software breakpoints not enabled"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + /* make sure we don't have any dangling breakpoints. This is vital upon + * GDB connect/disconnect + */ + arm7_9_clear_watchpoints(arm7_9); } if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1)) @@ -308,9 +330,29 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } if (breakpoint->type == BKPT_HARD) + { arm7_9->wp_available--; + + if (!arm7_9->wp0_used) + { + arm7_9->wp0_used = 1; + breakpoint->set = 1; + } + else if (!arm7_9->wp1_used) + { + arm7_9->wp1_used = 1; + breakpoint->set = 2; + } + else + { + LOG_ERROR("BUG: no hardware comparator available"); + } + } + - return ERROR_OK; + arm7_9->breakpoint_count++; + + return arm7_9_set_breakpoint(target, breakpoint); } int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) @@ -318,19 +360,17 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - if (breakpoint->set) - { - arm7_9_unset_breakpoint(target, breakpoint); - } + arm7_9_unset_breakpoint(target, breakpoint); if (breakpoint->type == BKPT_HARD) arm7_9->wp_available++; + + arm7_9->breakpoint_count--; + if (arm7_9->breakpoint_count==0) + { + /* make sure we don't have any dangling breakpoints */ + arm7_9_clear_watchpoints(arm7_9); + } return ERROR_OK; } @@ -457,12 +497,6 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - if (watchpoint->set) { arm7_9_unset_watchpoint(target, watchpoint); @@ -473,86 +507,11 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int arm7_9_enable_sw_bkpts(struct target_s *target) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - int retval; - if (arm7_9->sw_bkpts_enabled) - return ERROR_OK; - if (arm7_9->wp_available < 1) - { - LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - arm7_9->wp_available--; - - if (!arm7_9->wp0_used) - { - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - arm7_9->sw_bkpts_enabled = 1; - arm7_9->wp0_used = 3; - } - else if (!arm7_9->wp1_used) - { - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - arm7_9->sw_bkpts_enabled = 2; - arm7_9->wp1_used = 3; - } - else - { - LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); - return ERROR_FAIL; - } - - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints"); - return ERROR_FAIL; - }; - - return ERROR_OK; -} - -int arm7_9_disable_sw_bkpts(struct target_s *target) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - - if (!arm7_9->sw_bkpts_enabled) - return ERROR_OK; - - if (arm7_9->sw_bkpts_enabled == 1) - { - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); - arm7_9->sw_bkpts_enabled = 0; - arm7_9->wp0_used = 0; - arm7_9->wp_available++; - } - else if (arm7_9->sw_bkpts_enabled == 2) - { - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); - arm7_9->sw_bkpts_enabled = 0; - arm7_9->wp1_used = 0; - arm7_9->wp_available++; - } - - return ERROR_OK; -} int arm7_9_execute_sys_speed(struct target_s *target) { - int timeout; int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -568,7 +527,9 @@ int arm7_9_execute_sys_speed(struct target_s *target) } arm_jtag_set_instr(jtag_info, 0x4, NULL); - for (timeout=0; timeout<50; timeout++) + long long then=timeval_ms(); + int timeout; + while (!(timeout=((timeval_ms()-then)>1000))) { /* read debug status register */ embeddedice_read_reg(dbg_stat); @@ -577,9 +538,15 @@ int arm7_9_execute_sys_speed(struct target_s *target) if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)) && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1))) break; - usleep(100000); + if (debug_level>=3) + { + alive_sleep(100); + } else + { + keep_alive(); + } } - if (timeout == 50) + if (timeout) { LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size)); return ERROR_TARGET_TIMEOUT; @@ -767,7 +734,8 @@ int arm7_9_assert_reset(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); if (!(jtag_reset_config & RESET_HAS_SRST)) { @@ -815,18 +783,45 @@ int arm7_9_assert_reset(target_t *target) armv4_5_invalidate_core_regs(target); + if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)) + { + /* debug entry was already prepared in arm7_9_assert_reset() */ + target->debug_reason = DBG_REASON_DBGRQ; + } + return ERROR_OK; } int arm7_9_deassert_reset(target_t *target) { - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + int retval=ERROR_OK; + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + /* deassert reset lines */ jtag_add_reset(0, 0); - return ERROR_OK; + if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0) + { + LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset."); + /* set up embedded ice registers again */ + if ((retval=target->type->examine(target))!=ERROR_OK) + return retval; + + if ((retval=target_poll(target))!=ERROR_OK) + { + return retval; + } + + if ((retval=target_halt(target))!=ERROR_OK) + { + return retval; + } + + } + return retval; } int arm7_9_clear_halt(target_t *target) @@ -889,18 +884,24 @@ int arm7_9_soft_reset_halt(struct target_s *target) if ((retval=target_halt(target))!=ERROR_OK) return retval; - for (i=0; i<10; i++) + long long then=timeval_ms(); + int timeout; + while (!(timeout=((timeval_ms()-then)>1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0) break; embeddedice_read_reg(dbg_stat); if ((retval=jtag_execute_queue())!=ERROR_OK) return retval; - /* do not eat all CPU, time out after 1 se*/ - usleep(100*1000); - + if (debug_level>=3) + { + alive_sleep(100); + } else + { + keep_alive(); + } } - if (i==10) + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; @@ -961,11 +962,18 @@ int arm7_9_soft_reset_halt(struct target_s *target) int arm7_9_halt(target_t *target) { + if (target->state==TARGET_RESET) + { + LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()"); + return ERROR_OK; + } + armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); if (target->state == TARGET_HALTED) { @@ -978,24 +986,6 @@ int arm7_9_halt(target_t *target) LOG_WARNING("target was in unknown state when halt was requested"); } - if (target->state == TARGET_RESET) - { - if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst) - { - LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST"); - return ERROR_TARGET_FAILURE; - } - else - { - /* we came here in a reset_halt or reset_init sequence - * debug entry was already prepared in arm7_9_assert_reset() - */ - target->debug_reason = DBG_REASON_DBGRQ; - - return ERROR_OK; - } - } - if (arm7_9->use_dbgrq) { /* program EmbeddedICE Debug Control Register to assert DBGRQ @@ -1437,32 +1427,11 @@ void arm7_9_enable_breakpoints(struct target_s *target) /* set any pending breakpoints */ while (breakpoint) { - if (breakpoint->set == 0) - arm7_9_set_breakpoint(target, breakpoint); + arm7_9_set_breakpoint(target, breakpoint); breakpoint = breakpoint->next; } } -void arm7_9_disable_bkpts_and_wpts(struct target_s *target) -{ - breakpoint_t *breakpoint = target->breakpoints; - watchpoint_t *watchpoint = target->watchpoints; - - /* set any pending breakpoints */ - while (breakpoint) - { - if (breakpoint->set != 0) - arm7_9_unset_breakpoint(target, breakpoint); - breakpoint = breakpoint->next; - } - - while (watchpoint) - { - if (watchpoint->set != 0) - arm7_9_unset_watchpoint(target, watchpoint); - watchpoint = watchpoint->next; - } -} int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) { @@ -2211,14 +2180,22 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe target_halt(target); - for (i=0; i<100; i++) + long long then=timeval_ms(); + int timeout; + while (!(timeout=((timeval_ms()-then)>100))) { target_poll(target); if (target->state == TARGET_HALTED) break; - usleep(1000); /* sleep 1ms */ + if (debug_level>=3) + { + alive_sleep(100); + } else + { + keep_alive(); + } } - if (i == 100) + if (timeout) { LOG_ERROR("bulk write timed out, target not halted"); return ERROR_TARGET_TIMEOUT; @@ -2389,8 +2366,6 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx) register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register "); - register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints "); - register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) "); register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command, COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests "); register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command, @@ -2529,95 +2504,6 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char return ERROR_OK; } -int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - - if (target->state != TARGET_HALTED) - { - LOG_ERROR("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; - } - - if (argc == 0) - { - command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled"); - return ERROR_OK; - } - - if (strcmp("enable", args[0]) == 0) - { - if (arm7_9->sw_bkpts_use_wp) - { - arm7_9_enable_sw_bkpts(target); - } - else - { - arm7_9->sw_bkpts_enabled = 1; - } - } - else if (strcmp("disable", args[0]) == 0) - { - if (arm7_9->sw_bkpts_use_wp) - { - arm7_9_disable_sw_bkpts(target); - } - else - { - arm7_9->sw_bkpts_enabled = 0; - } - } - else - { - command_print(cmd_ctx, "usage: arm7_9 sw_bkpts "); - } - - command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled"); - - return ERROR_OK; -} - -int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; - } - - if ((argc >= 1) && (strcmp("enable", args[0]) == 0)) - { - arm7_9->force_hw_bkpts = 1; - if (arm7_9->sw_bkpts_use_wp) - { - arm7_9_disable_sw_bkpts(target); - } - } - else if ((argc >= 1) && (strcmp("disable", args[0]) == 0)) - { - arm7_9->force_hw_bkpts = 0; - } - else - { - command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts "); - } - - command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled"); - - return ERROR_OK; -} int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { @@ -2725,10 +2611,13 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) arm7_9->common_magic = ARM7_9_COMMON_MAGIC; arm_jtag_setup_connection(&arm7_9->jtag_info); - arm7_9->wp_available = 2; + arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */ + arm7_9->wp_available_max = 2; + arm7_9->sw_breakpoints_added = 0; + arm7_9->breakpoint_count = 0; arm7_9->wp0_used = 0; arm7_9->wp1_used = 0; - arm7_9->force_hw_bkpts = 0; + arm7_9->wp1_used_default = 0; arm7_9->use_dbgrq = 0; arm7_9->etm_ctx = NULL;