X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=225dd9ecb2e7063d3296c0c8c758c8829c77e8c2;hb=809a796209b5660bd4b968a48794211871f686b9;hp=8e2adcc6bb0805452a0c55529bcc1ebb59b254b0;hpb=6954dc72398dcae88aaae39c7476cb98a2f1fccf;p=openocd.git diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 8e2adcc6bb..225dd9ecb2 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -2,9 +2,12 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyvind.harboe@zylin.com * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -35,6 +38,7 @@ #include "log.h" #include "arm7_9_common.h" #include "breakpoints.h" +#include "time_support.h" #include #include @@ -59,15 +63,14 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -/* FIX!!! this needs to be overrideable by e.g. fereceon*/ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) { embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); arm7_9->sw_breakpoints_added = 0; arm7_9->wp0_used = 0; - arm7_9->wp1_used = 0; - arm7_9->wp_available = 2; + arm7_9->wp1_used = arm7_9->wp1_used_default; + arm7_9->wp_available = arm7_9->wp_available_max; return jtag_execute_queue(); } @@ -85,7 +88,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } arm7_9->wp_available--; - + /* pick a breakpoint unit */ if (!arm7_9->wp0_used) { @@ -205,11 +208,11 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK) return retval; - + /* did we already set this breakpoint? */ if (breakpoint->set) return ERROR_OK; - + if (breakpoint->length == 4) { u32 verify = 0xffffffff; @@ -308,13 +311,13 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - + if (arm7_9->breakpoint_count==0) { - /* make sure we don't have any dangling breakpoints. This is vital upon - * GDB connect/disconnect + /* make sure we don't have any dangling breakpoints. This is vital upon + * GDB connect/disconnect */ - arm7_9_clear_watchpoints(arm7_9); + arm7_9_clear_watchpoints(arm7_9); } if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1)) @@ -332,7 +335,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) { arm7_9->wp_available--; - + if (!arm7_9->wp0_used) { arm7_9->wp0_used = 1; @@ -348,10 +351,10 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_ERROR("BUG: no hardware comparator available"); } } - + arm7_9->breakpoint_count++; - + return arm7_9_set_breakpoint(target, breakpoint); } @@ -364,12 +367,12 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) arm7_9->wp_available++; - + arm7_9->breakpoint_count--; if (arm7_9->breakpoint_count==0) { /* make sure we don't have any dangling breakpoints */ - arm7_9_clear_watchpoints(arm7_9); + arm7_9_clear_watchpoints(arm7_9); } return ERROR_OK; @@ -512,7 +515,6 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) int arm7_9_execute_sys_speed(struct target_s *target) { - int timeout; int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -528,7 +530,9 @@ int arm7_9_execute_sys_speed(struct target_s *target) } arm_jtag_set_instr(jtag_info, 0x4, NULL); - for (timeout=0; timeout<50; timeout++) + long long then=timeval_ms(); + int timeout; + while (!(timeout=((timeval_ms()-then)>1000))) { /* read debug status register */ embeddedice_read_reg(dbg_stat); @@ -537,9 +541,15 @@ int arm7_9_execute_sys_speed(struct target_s *target) if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)) && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1))) break; - usleep(100000); + if (debug_level>=3) + { + alive_sleep(100); + } else + { + keep_alive(); + } } - if (timeout == 50) + if (timeout) { LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size)); return ERROR_TARGET_TIMEOUT; @@ -727,7 +737,8 @@ int arm7_9_assert_reset(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); if (!(jtag_reset_config & RESET_HAS_SRST)) { @@ -780,7 +791,7 @@ int arm7_9_assert_reset(target_t *target) /* debug entry was already prepared in arm7_9_assert_reset() */ target->debug_reason = DBG_REASON_DBGRQ; } - + return ERROR_OK; } @@ -788,7 +799,9 @@ int arm7_9_assert_reset(target_t *target) int arm7_9_deassert_reset(target_t *target) { int retval=ERROR_OK; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + /* deassert reset lines */ jtag_add_reset(0, 0); @@ -804,12 +817,12 @@ int arm7_9_deassert_reset(target_t *target) { return retval; } - + if ((retval=target_halt(target))!=ERROR_OK) { return retval; } - + } return retval; } @@ -874,18 +887,24 @@ int arm7_9_soft_reset_halt(struct target_s *target) if ((retval=target_halt(target))!=ERROR_OK) return retval; - for (i=0; i<10; i++) + long long then=timeval_ms(); + int timeout; + while (!(timeout=((timeval_ms()-then)>1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0) break; embeddedice_read_reg(dbg_stat); if ((retval=jtag_execute_queue())!=ERROR_OK) return retval; - /* do not eat all CPU, time out after 1 se*/ - usleep(100*1000); - + if (debug_level>=3) + { + alive_sleep(100); + } else + { + keep_alive(); + } } - if (i==10) + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; @@ -956,7 +975,8 @@ int arm7_9_halt(target_t *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); if (target->state == TARGET_HALTED) { @@ -1801,6 +1821,8 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count reg[0] = address; arm7_9->write_core_regs(target, 0x1, reg); + int j=0; + switch (size) { case 4: @@ -1828,6 +1850,11 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count /* advance buffer, count number of accesses */ buffer += thisrun_accesses * 4; num_accesses += thisrun_accesses; + + if ((j++%1024)==0) + { + keep_alive(); + } } break; case 2: @@ -1856,6 +1883,11 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count /* advance buffer, count number of accesses */ buffer += thisrun_accesses * 2; num_accesses += thisrun_accesses; + + if ((j++%1024)==0) + { + keep_alive(); + } } break; case 1: @@ -1884,6 +1916,11 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count /* advance buffer, count number of accesses */ buffer += thisrun_accesses * 1; num_accesses += thisrun_accesses; + + if ((j++%1024)==0) + { + keep_alive(); + } } break; default: @@ -2087,20 +2124,61 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun return ERROR_OK; } +static int dcc_count; +static u8 *dcc_buffer; + + +static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info) +{ + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + int little=target->endianness==TARGET_LITTLE_ENDIAN; + int count=dcc_count; + u8 *buffer=dcc_buffer; + if (count>2) + { + /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the + core function repeated. + */ + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + buffer+=4; + + embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; + u8 reg_addr = ice_reg->addr & 0x1f; + int chain_pos = ice_reg->jtag_info->chain_pos; + + embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2); + buffer += (count-2)*4; + + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + } else + { + int i; + for (i = 0; i < count; i++) + { + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + buffer += 4; + } + } + + target_halt(target); + return target_wait_state(target, TARGET_HALTED, 500); +} + + static const u32 dcc_code[] = { /* MRC TST BNE MRC STR B */ 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9 }; +int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)); + + int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - enum armv4_5_state core_state = armv4_5->core_state; - u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); - u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32); - u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); int i; if (!arm7_9->dcc_downloads) @@ -2128,67 +2206,38 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf); } - buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address); - armv4_5->core_cache->reg_list[0].valid = 1; - armv4_5->core_cache->reg_list[0].dirty = 1; - armv4_5->core_state = ARMV4_5_STATE_ARM; + armv4_5_algorithm_t armv4_5_info; + reg_param_t reg_params[1]; - arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1); + armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; + armv4_5_info.core_mode = ARMV4_5_MODE_SVC; + armv4_5_info.core_state = ARMV4_5_STATE_ARM; - int little=target->endianness==TARGET_LITTLE_ENDIAN; - if (count>2) - { - /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the - core function repeated. - */ - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - buffer+=4; + init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); - embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; - u8 reg_addr = ice_reg->addr & 0x1f; - int chain_pos = ice_reg->jtag_info->chain_pos; + buf_set_u32(reg_params[0].value, 0, 32, address); - embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2); - buffer += (count-2)*4; + //armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, + // int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)) + int retval; + dcc_count=count; + dcc_buffer=buffer; + retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params, + arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - } else + if (retval==ERROR_OK) { - for (i = 0; i < count; i++) + u32 endaddress=buf_get_u32(reg_params[0].value, 0, 32); + if (endaddress!=(address+count*4)) { - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - buffer += 4; + LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress); + retval=ERROR_FAIL; } } - target_halt(target); - - for (i=0; i<100; i++) - { - target_poll(target); - if (target->state == TARGET_HALTED) - break; - usleep(1000); /* sleep 1ms */ - } - if (i == 100) - { - LOG_ERROR("bulk write timed out, target not halted"); - return ERROR_TARGET_TIMEOUT; - } - - /* restore target state */ - buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0); - armv4_5->core_cache->reg_list[0].valid = 1; - armv4_5->core_cache->reg_list[0].dirty = 1; - buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1); - armv4_5->core_cache->reg_list[1].valid = 1; - armv4_5->core_cache->reg_list[1].dirty = 1; - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc); - armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_state = core_state; + destroy_reg_param(®_params[0]); - return ERROR_OK; + return retval; } int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) @@ -2235,7 +2284,12 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* /* convert flash writing code into a buffer in target endianness */ for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++) - target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]); + { + if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]))!=ERROR_OK) + { + return retval; + } + } armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; armv4_5_info.core_mode = ARMV4_5_MODE_SVC; @@ -2586,11 +2640,13 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) arm7_9->common_magic = ARM7_9_COMMON_MAGIC; arm_jtag_setup_connection(&arm7_9->jtag_info); - arm7_9->wp_available = 2; + arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */ + arm7_9->wp_available_max = 2; arm7_9->sw_breakpoints_added = 0; arm7_9->breakpoint_count = 0; arm7_9->wp0_used = 0; arm7_9->wp1_used = 0; + arm7_9->wp1_used_default = 0; arm7_9->use_dbgrq = 0; arm7_9->etm_ctx = NULL;