X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=e7672b45a0a7dd67fc768c0961d309ed2f939368;hb=ce58ab9a4ef7f014eac4d2e30d2b54b2c3e53895;hp=d900d8ae23981fab090b127b0a69d40920deeaba;hpb=177bbd8891ae737ea7f8c0791a6236f72cedee40;p=openocd.git diff --git a/src/target/arm720t.c b/src/target/arm720t.c index d900d8ae23..e7672b45a0 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -25,9 +25,10 @@ #endif #include "arm720t.h" -#include "time_support.h" +#include #include "target_type.h" #include "register.h" +#include "arm_opcodes.h" /* @@ -53,22 +54,19 @@ static int arm720t_scan_cp15(struct target *target, buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); - jtag_set_end_state(TAP_DRPAUSE); - if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) + if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK) { return retval; } - if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK) + if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK) { return retval; } - fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &instruction_buf; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = out_buf; fields[1].in_value = NULL; @@ -76,15 +74,15 @@ static int arm720t_scan_cp15(struct target *target, if (in) { fields[1].in_value = (uint8_t *)in; - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); jtag_add_callback(arm7flip32, (jtag_callback_data_t)in); } else { - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); } if (clock) - jtag_add_runtest(0, jtag_get_end_state()); + jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -234,14 +232,8 @@ static int arm720t_arch_state(struct target *target) armv4_5 = &arm720t->arm7_9_common.armv4_5_common; - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, Cache: %s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , - arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->cpsr->value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + arm_arch_state(target); + LOG_USER("MMU: %s, Cache: %s", state[arm720t->armv4_5_mmu.mmu_enabled], state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]); @@ -260,11 +252,20 @@ static int arm720_mmu(struct target *target, int *enabled) } static int arm720_virt2phys(struct target *target, - uint32_t virt, uint32_t *phys) + uint32_t virtual, uint32_t *physical) { - /** @todo Implement this! */ - LOG_ERROR("%s: not implemented", __func__); - return ERROR_FAIL; + int type; + uint32_t cb; + int domain; + uint32_t ap; + struct arm720t_common *arm720t = target_to_arm720(target); + + uint32_t ret; + int retval = armv4_5_mmu_translate_va(target, &arm720t->armv4_5_mmu, virtual, &type, &cb, &domain, &ap, &ret); + if (retval != ERROR_OK) + return retval; + *physical = ret; + return ERROR_OK; } static int arm720t_read_memory(struct target *target, @@ -356,9 +357,9 @@ static int arm720t_soft_reset_halt(struct target *target) armv4_5->cpsr->dirty = 1; /* start fetching from 0x0 */ - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; + buf_set_u32(armv4_5->pc->value, 0, 32, 0x0); + armv4_5->pc->dirty = 1; + armv4_5->pc->valid = 1; arm720t_disable_mmu_caches(target, 1, 1, 1); arm720t->armv4_5_mmu.mmu_enabled = 0; @@ -481,7 +482,10 @@ COMMAND_HANDLER(arm720t_handle_cp15_command) return ERROR_OK; } -static int arm720t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int arm720t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value) { if (cpnum!=15) { @@ -489,11 +493,17 @@ static int arm720t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t return ERROR_FAIL; } - return arm720t_read_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value); + /* read "to" r0 */ + return arm720t_read_cp15(target, + ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + value); } -static int arm720t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int arm720t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value) { if (cpnum!=15) { @@ -501,7 +511,10 @@ static int arm720t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t return ERROR_FAIL; } - return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value); + /* write "from" r0 */ + return arm720t_write_cp15(target, + ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + value); } static const struct command_registration arm720t_exec_command_handlers[] = { @@ -509,8 +522,10 @@ static const struct command_registration arm720t_exec_command_handlers[] = { .name = "cp15", .handler = arm720t_handle_cp15_command, .mode = COMMAND_EXEC, - .usage = " [value]", - .help = "display/modify cp15 register", + /* prefer using less error-prone "arm mcr" or "arm mrc" */ + .help = "display/modify cp15 register using ARM opcode" + " (DEPRECATED)", + .usage = "instruction [value]", }, COMMAND_REGISTRATION_DONE }; @@ -544,7 +559,7 @@ struct target_type arm720t_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm720t_soft_reset_halt, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm720t_read_memory, .write_memory = arm7_9_write_memory, @@ -569,4 +584,5 @@ struct target_type arm720t_target = .target_create = arm720t_target_create, .init_target = arm720t_init_target, .examine = arm7_9_examine, + .check_reset = arm7_9_check_reset, };