X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=ac7e4888832bb9ea3ccceb1f34c8055662ebb4e9;hb=ff810723e051ed1f86cffcb565ade6b4d1fc50c8;hp=8ef7114e637eecb4644f93f4981e58db0ee92a02;hpb=056fcdb540f0ab9a404f3b5de72fd707eb146603;p=openocd.git diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 8ef7114e63..ac7e488883 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -27,6 +27,7 @@ #include "arm720t.h" #include "time_support.h" #include "target_type.h" +#include "register.h" /* @@ -38,7 +39,7 @@ #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -static int arm720t_scan_cp15(target_t *target, +static int arm720t_scan_cp15(struct target *target, uint32_t out, uint32_t *in, int instruction, int clock) { int retval; @@ -48,7 +49,7 @@ static int arm720t_scan_cp15(target_t *target, uint8_t out_buf[4]; uint8_t instruction_buf = instruction; - jtag_info = &arm720t->arm7tdmi_common.arm7_9_common.jtag_info; + jtag_info = &arm720t->arm7_9_common.jtag_info; buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); @@ -102,7 +103,7 @@ static int arm720t_scan_cp15(target_t *target, return ERROR_OK; } -static int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value) +static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value) { /* fetch CP15 opcode */ arm720t_scan_cp15(target, opcode, NULL, 1, 1); @@ -119,7 +120,7 @@ static int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value) return ERROR_OK; } -static int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value) +static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value) { /* fetch CP15 opcode */ arm720t_scan_cp15(target, opcode, NULL, 1, 1); @@ -135,7 +136,7 @@ static int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value) return ERROR_OK; } -static uint32_t arm720t_get_ttb(target_t *target) +static uint32_t arm720t_get_ttb(struct target *target) { uint32_t ttb = 0x0; @@ -147,7 +148,7 @@ static uint32_t arm720t_get_ttb(target_t *target) return ttb; } -static void arm720t_disable_mmu_caches(target_t *target, +static void arm720t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; @@ -165,7 +166,7 @@ static void arm720t_disable_mmu_caches(target_t *target, arm720t_write_cp15(target, 0xee010f10, cp15_control); } -static void arm720t_enable_mmu_caches(target_t *target, +static void arm720t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; @@ -183,7 +184,7 @@ static void arm720t_enable_mmu_caches(target_t *target, arm720t_write_cp15(target, 0xee010f10, cp15_control); } -static void arm720t_post_debug_entry(target_t *target) +static void arm720t_post_debug_entry(struct target *target) { struct arm720t_common *arm720t = target_to_arm720(target); @@ -202,7 +203,7 @@ static void arm720t_post_debug_entry(target_t *target) jtag_execute_queue(); } -static void arm720t_pre_restore_context(target_t *target) +static void arm720t_pre_restore_context(struct target *target) { struct arm720t_common *arm720t = target_to_arm720(target); @@ -211,7 +212,7 @@ static void arm720t_pre_restore_context(target_t *target) arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg); } -static int arm720t_verify_pointer(struct command_context_s *cmd_ctx, +static int arm720t_verify_pointer(struct command_context *cmd_ctx, struct arm720t_common *arm720t) { if (arm720t->common_magic != ARM720T_COMMON_MAGIC) { @@ -221,7 +222,7 @@ static int arm720t_verify_pointer(struct command_context_s *cmd_ctx, return ERROR_OK; } -static int arm720t_arch_state(struct target_s *target) +static int arm720t_arch_state(struct target *target) { struct arm720t_common *arm720t = target_to_arm720(target); struct armv4_5_common_s *armv4_5; @@ -231,15 +232,15 @@ static int arm720t_arch_state(struct target_s *target) "disabled", "enabled" }; - armv4_5 = &arm720t->arm7tdmi_common.arm7_9_common.armv4_5_common; + armv4_5 = &arm720t->arm7_9_common.armv4_5_common; LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" "MMU: %s, Cache: %s", armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), + arm_mode_name(armv4_5->core_mode), + buf_get_u32(armv4_5->cpsr->value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm720t->armv4_5_mmu.mmu_enabled], state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]); @@ -247,7 +248,7 @@ static int arm720t_arch_state(struct target_s *target) return ERROR_OK; } -static int arm720_mmu(struct target_s *target, int *enabled) +static int arm720_mmu(struct target *target, int *enabled) { if (target->state != TARGET_HALTED) { LOG_ERROR("%s: target not halted", __func__); @@ -258,7 +259,7 @@ static int arm720_mmu(struct target_s *target, int *enabled) return ERROR_OK; } -static int arm720_virt2phys(struct target_s *target, +static int arm720_virt2phys(struct target *target, uint32_t virt, uint32_t *phys) { /** @todo Implement this! */ @@ -266,7 +267,7 @@ static int arm720_virt2phys(struct target_s *target, return ERROR_FAIL; } -static int arm720t_read_memory(struct target_s *target, +static int arm720t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -284,7 +285,7 @@ static int arm720t_read_memory(struct target_s *target, return retval; } -static int arm720t_read_phys_memory(struct target_s *target, +static int arm720t_read_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct arm720t_common *arm720t = target_to_arm720(target); @@ -292,7 +293,7 @@ static int arm720t_read_phys_memory(struct target_s *target, return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer); } -static int arm720t_write_phys_memory(struct target_s *target, +static int arm720t_write_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct arm720t_common *arm720t = target_to_arm720(target); @@ -300,14 +301,14 @@ static int arm720t_write_phys_memory(struct target_s *target, return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer); } -static int arm720t_soft_reset_halt(struct target_s *target) +static int arm720t_soft_reset_halt(struct target *target) { int retval = ERROR_OK; struct arm720t_common *arm720t = target_to_arm720(target); - reg_t *dbg_stat = &arm720t->arm7tdmi_common.arm7_9_common + struct reg *dbg_stat = &arm720t->arm7_9_common .eice_cache->reg_list[EICE_DBG_STAT]; - struct armv4_5_common_s *armv4_5 = &arm720t->arm7tdmi_common - .arm7_9_common.armv4_5_common; + struct armv4_5_common_s *armv4_5 = &arm720t->arm7_9_common + .armv4_5_common; if ((retval = target_halt(target)) != ERROR_OK) { @@ -346,18 +347,20 @@ static int arm720t_soft_reset_halt(struct target_s *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; + + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); + armv4_5->cpsr->dirty = 1; + armv4_5->core_state = ARMV4_5_STATE_ARM; /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; - arm720t_disable_mmu_caches(target, 1, 1, 1); arm720t->armv4_5_mmu.mmu_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; @@ -371,18 +374,17 @@ static int arm720t_soft_reset_halt(struct target_s *target) return ERROR_OK; } -static int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target) { return arm7tdmi_init_target(cmd_ctx, target); } -static int arm720t_init_arch_info(target_t *target, +static int arm720t_init_arch_info(struct target *target, struct arm720t_common *arm720t, struct jtag_tap *tap) { - struct arm7tdmi_common *arm7tdmi = &arm720t->arm7tdmi_common; - struct arm7_9_common *arm7_9 = &arm7tdmi->arm7_9_common; + struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common; - arm7tdmi_init_arch_info(target, arm7tdmi, tap); + arm7tdmi_init_arch_info(target, arm7_9, tap); arm720t->common_magic = ARM720T_COMMON_MAGIC; @@ -401,45 +403,45 @@ static int arm720t_init_arch_info(target_t *target, return ERROR_OK; } -static int arm720t_target_create(struct target_s *target, Jim_Interp *interp) +static int arm720t_target_create(struct target *target, Jim_Interp *interp) { struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t)); - arm720t->arm7tdmi_common.arm7_9_common.armv4_5_common.is_armv4 = true; + arm720t->arm7_9_common.armv4_5_common.is_armv4 = true; return arm720t_init_arch_info(target, arm720t, target->tap); } COMMAND_HANDLER(arm720t_handle_cp15_command) { int retval; - target_t *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm720t_common *arm720t = target_to_arm720(target); struct arm_jtag *jtag_info; - retval = arm720t_verify_pointer(cmd_ctx, arm720t); + retval = arm720t_verify_pointer(CMD_CTX, arm720t); if (retval != ERROR_OK) return retval; - jtag_info = &arm720t->arm7tdmi_common.arm7_9_common.jtag_info; + jtag_info = &arm720t->arm7_9_common.jtag_info; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (argc >= 1) + if (CMD_ARGC >= 1) { uint32_t opcode; - COMMAND_PARSE_NUMBER(u32, args[0], opcode); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode); - if (argc == 1) + if (CMD_ARGC == 1) { uint32_t value; if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } @@ -448,26 +450,26 @@ COMMAND_HANDLER(arm720t_handle_cp15_command) return retval; } - command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); } - else if (argc == 2) + else if (CMD_ARGC == 2) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); } } return ERROR_OK; } -static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int arm720t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { if (cpnum!=15) { @@ -479,7 +481,7 @@ static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, } -static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int arm720t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { if (cpnum!=15) { @@ -490,10 +492,10 @@ static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value); } -static int arm720t_register_commands(struct command_context_s *cmd_ctx) +static int arm720t_register_commands(struct command_context *cmd_ctx) { int retval; - command_t *arm720t_cmd; + struct command *arm720t_cmd; retval = arm7_9_register_commands(cmd_ctx); @@ -510,7 +512,7 @@ static int arm720t_register_commands(struct command_context_s *cmd_ctx) } /** Holds methods for ARM720 targets. */ -target_type_t arm720t_target = +struct target_type arm720t_target = { .name = "arm720t", @@ -535,8 +537,9 @@ target_type_t arm720t_target = .virt2phys = arm720_virt2phys, .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -548,8 +551,7 @@ target_type_t arm720t_target = .register_commands = arm720t_register_commands, .target_create = arm720t_target_create, .init_target = arm720t_init_target, - .examine = arm7tdmi_examine, + .examine = arm7_9_examine, .mrc = arm720t_mrc, .mcr = arm720t_mcr, - };