X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=71440ebedbf5e78f86d6d44932c7872df286c76c;hb=1e5daf5886999a8ff01a4957e17c1466d76e022d;hp=0dbfdb41b663ff3c3445790a8546eb79b2c75f35;hpb=68b05c55759970657c32607b3ce27c42e65cdad0;p=openocd.git diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 0dbfdb41b6..71440ebedb 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -23,6 +23,7 @@ #include "arm720t.h" #include "time_support.h" +#include "target_type.h" #if 0 @@ -33,17 +34,16 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx); int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); /* forward declarations */ int arm720t_target_create(struct target_s *target,Jim_Interp *interp); int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm720t_quit(void); int arm720t_arch_state(struct target_s *target); -int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); -int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); +int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); +int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); +int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); +int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); int arm720t_soft_reset_halt(struct target_s *target); target_type_t arm720t_target = @@ -65,6 +65,8 @@ target_type_t arm720t_target = .read_memory = arm720t_read_memory, .write_memory = arm720t_write_memory, + .read_phys_memory = arm720t_read_phys_memory, + .write_phys_memory = arm720t_write_phys_memory, .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, .blank_check_memory = arm7_9_blank_check_memory, @@ -81,26 +83,27 @@ target_type_t arm720t_target = .init_target = arm720t_init_target, .examine = arm7tdmi_examine, .quit = arm720t_quit + }; -int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock) +int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruction, int clock) { int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; scan_field_t fields[2]; - u8 out_buf[4]; - u8 instruction_buf = instruction; + uint8_t out_buf[4]; + uint8_t instruction_buf = instruction; buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); - jtag_add_end_state(TAP_DRPAUSE); - if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) + jtag_set_end_state(TAP_DRPAUSE); + if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; } - if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK) + if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK) { return retval; } @@ -117,20 +120,19 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c if (in) { - u8 tmp[4]; - fields[1].in_value = tmp; - jtag_add_dr_scan_now(2, fields, TAP_INVALID); - *in=flip_u32(le_to_h_u32(tmp), 32); + fields[1].in_value = (uint8_t *)in; + jtag_add_dr_scan(2, fields, jtag_get_end_state()); + jtag_add_callback(arm7flip32, (jtag_callback_data_t)in); } else { - jtag_add_dr_scan(2, fields, TAP_INVALID); + jtag_add_dr_scan(2, fields, jtag_get_end_state()); } if (clock) - jtag_add_runtest(0, TAP_INVALID); + jtag_add_runtest(0, jtag_get_end_state()); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -140,13 +142,13 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c else LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); #else - LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); + LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock); #endif return ERROR_OK; } -int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value) +int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value) { /* fetch CP15 opcode */ arm720t_scan_cp15(target, opcode, NULL, 1, 1); @@ -163,7 +165,7 @@ int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value) return ERROR_OK; } -int arm720t_write_cp15(target_t *target, u32 opcode, u32 value) +int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value) { /* fetch CP15 opcode */ arm720t_scan_cp15(target, opcode, NULL, 1, 1); @@ -179,9 +181,9 @@ int arm720t_write_cp15(target_t *target, u32 opcode, u32 value) return ERROR_OK; } -u32 arm720t_get_ttb(target_t *target) +uint32_t arm720t_get_ttb(target_t *target) { - u32 ttb = 0x0; + uint32_t ttb = 0x0; arm720t_read_cp15(target, 0xee120f10, &ttb); jtag_execute_queue(); @@ -193,7 +195,7 @@ u32 arm720t_get_ttb(target_t *target) void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) { - u32 cp15_control; + uint32_t cp15_control; /* read cp15 control register */ arm720t_read_cp15(target, 0xee110f10, &cp15_control); @@ -210,7 +212,7 @@ void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) { - u32 cp15_control; + uint32_t cp15_control; /* read cp15 control register */ arm720t_read_cp15(target, 0xee110f10, &cp15_control); @@ -235,7 +237,7 @@ void arm720t_post_debug_entry(target_t *target) /* examine cp15 control reg */ arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg); jtag_execute_queue(); - LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg); + LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg); arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0; @@ -316,10 +318,10 @@ int arm720t_arch_state(struct target_s *target) } LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8x pc: 0x%8.8x\n" + "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" "MMU: %s, Cache: %s", armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name , + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), @@ -329,7 +331,7 @@ int arm720t_arch_state(struct target_s *target) return ERROR_OK; } -int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -349,7 +351,7 @@ int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 coun return retval; } -int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -359,6 +361,28 @@ int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou return retval; } + +int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +{ + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; + arm720t_common_t *arm720t = arm7tdmi->arch_info; + + return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer); +} + +int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +{ + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; + arm720t_common_t *arm720t = arm7tdmi->arch_info; + + return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer); +} + + int arm720t_soft_reset_halt(struct target_s *target) { int retval = ERROR_OK; @@ -373,9 +397,9 @@ int arm720t_soft_reset_halt(struct target_s *target) return retval; } - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then) > 1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { @@ -388,7 +412,7 @@ int arm720t_soft_reset_halt(struct target_s *target) { break; } - if (debug_level>=3) + if (debug_level >= 3) { alive_sleep(100); } else @@ -487,15 +511,6 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx) arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands"); register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); - register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa "); - - register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words [count]"); - register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words [count]"); - register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes [count]"); - - register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word "); - register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word "); - register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte "); return ERROR_OK; } @@ -527,14 +542,14 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch /* one or more argument, access a single register (write if second argument is given */ if (argc >= 1) { - u32 opcode = strtoul(args[0], NULL, 0); + uint32_t opcode = strtoul(args[0], NULL, 0); if (argc == 1) { - u32 value; + uint32_t value; if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode); + command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } @@ -543,97 +558,19 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch return retval; } - command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value); + command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); } else if (argc == 2) { - u32 value = strtoul(args[1], NULL, 0); + uint32_t value = strtoul(args[1], NULL, 0); if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode); + command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value); + command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); } } return ERROR_OK; } - -int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm7tdmi_common_t *arm7tdmi; - arm720t_common_t *arm720t; - arm_jtag_t *jtag_info; - - if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM720t target"); - return ERROR_OK; - } - - jtag_info = &arm7_9->jtag_info; - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } - - return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); -} - -int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm7tdmi_common_t *arm7tdmi; - arm720t_common_t *arm720t; - arm_jtag_t *jtag_info; - - if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM720t target"); - return ERROR_OK; - } - - jtag_info = &arm7_9->jtag_info; - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } - - return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); -} - -int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm7tdmi_common_t *arm7tdmi; - arm720t_common_t *arm720t; - arm_jtag_t *jtag_info; - - if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM720t target"); - return ERROR_OK; - } - - jtag_info = &arm7_9->jtag_info; - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } - - return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); -}