X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11_dbgtap.c;h=fa127c640b0737622f1e8ac715cab4f4a452c469;hb=7c7fed0283e5c6e434de94af443218ef78175e87;hp=7360717625c8c85c780161e85e7628f0612afb0a;hpb=4866c8ed25ebc915db51824046589547f1f8585d;p=openocd.git diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 7360717625..fa127c640b 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -36,6 +36,13 @@ #define JTAG_DEBUG(expr ...) do {} while(0) #endif +/* +This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The +behavior of the FTDI driver IIRC was to go via RTI. + +Conversely there may be other places in this code where the ARM11 code relies +on the driver to hit through RTI when coming from Update-?R. +*/ tap_state_t arm11_move_pi_to_si_via_ci[] = { TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT @@ -80,12 +87,6 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo { field->tap = arm11->jtag_info.tap; field->num_bits = num_bits; - field->out_mask = NULL; - field->in_check_mask = NULL; - field->in_check_value = NULL; - field->in_handler = NULL; - field->in_handler_priv = NULL; - field->out_value = out_data; field->in_value = in_data; } @@ -124,7 +125,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) * arm11_add_debug_SCAN_N(). * */ -static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field) +static void arm11_in_handler_SCAN_N(u8 *in_value) { /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */ u8 v = *in_value & 0x1F; @@ -132,11 +133,10 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s if (v != 0x10) { LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); - return ERROR_FAIL; + jtag_set_error(ERROR_FAIL); } JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); - return ERROR_OK; } /** Select and write to Scan Chain Register (SCREG) @@ -171,11 +171,14 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state) scan_field_t field; - arm11_setup_field(arm11, 5, &chain, NULL, &field); - - field.in_handler = arm11_in_handler_SCAN_N; + u8 tmp[1]; + arm11_setup_field(arm11, 5, &chain, &tmp, &field); arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state); + + jtag_execute_queue_noclear(); + + arm11_in_handler_SCAN_N(tmp); } /** Write an instruction into the ITR register @@ -229,11 +232,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value) arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - { - return retval; - } + CHECK_RETVAL(jtag_execute_queue()); if (arm11->last_dscr != dscr) JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr); @@ -242,7 +241,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value) *value=dscr; - return retval; + return ERROR_OK; } /** Write the Debug Status and Control Register (DSCR) @@ -254,7 +253,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value) * * \remarks This is a stand-alone function that executes the JTAG command queue. */ -void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) +int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) { arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); @@ -266,11 +265,13 @@ void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - jtag_execute_queue(); + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr); arm11->last_dscr = dscr; + + return ERROR_OK; } @@ -365,7 +366,7 @@ void arm11_run_instr_data_finish(arm11_common_t * arm11) * \param count Number of opcodes to execute * */ -void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) +int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -379,12 +380,14 @@ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE); - jtag_execute_queue(); + CHECK_RETVAL(jtag_execute_queue()); if (flag) break; } } + + return ERROR_OK; } /** Execute one instruction via ITR @@ -414,7 +417,7 @@ void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode) * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -439,7 +442,8 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data Data = *data; arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE); - jtag_execute_queue(); + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry); } @@ -455,11 +459,14 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data Data = 0; arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - jtag_execute_queue(); + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); } while (!Ready); + + return ERROR_OK; } /** JTAG path for arm11_run_instr_data_to_core_noack @@ -472,6 +479,8 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data * layer (FT2232) that is long enough to finish execution on * the core but still shorter than any manually inducible delays. * + * To disable this code, try "memwrite burst false" + * */ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = { @@ -495,7 +504,7 @@ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -536,21 +545,22 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - jtag_execute_queue(); + CHECK_RETVAL(jtag_execute_queue()); size_t error_count = 0; - {size_t i; - for (i = 0; i < asizeof(Readies); i++) + for (size_t i = 0; i < asizeof(Readies); i++) { if (Readies[i] != 1) { error_count++; } - }} + } if (error_count) LOG_ERROR("Transfer errors " ZU, error_count); + + return ERROR_OK; } @@ -565,9 +575,9 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * \param data Data word to be passed to the core via DTR * */ -void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data) +int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data) { - arm11_run_instr_data_to_core(arm11, opcode, &data, 1); + return arm11_run_instr_data_to_core(arm11, opcode, &data, 1); } @@ -584,7 +594,7 @@ void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data) * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -607,7 +617,8 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da do { arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE); - jtag_execute_queue(); + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); } @@ -615,6 +626,8 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da *data++ = Data; } + + return ERROR_OK; } /** Execute one instruction via ITR @@ -666,7 +679,7 @@ void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * \param count Number of instructions in the list. * */ -void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count) +int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count) { arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT); @@ -685,8 +698,7 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1); arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2); - {size_t i; - for (i = 0; i < count + 1; i++) + for (size_t i = 0; i < count + 1; i++) { if (i < count) { @@ -706,7 +718,8 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW); arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE); - jtag_execute_queue(); + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready); } @@ -731,13 +744,14 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t } } } - }} + } - {size_t i; - for (i = 0; i < count; i++) + for (size_t i = 0; i < count; i++) { JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value); - }} + } + + return ERROR_OK; } /** Clear VCR and all breakpoints and watchpoints via scan chain 7 @@ -750,22 +764,19 @@ void arm11_sc7_clear_vbw(arm11_common_t * arm11) arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1]; arm11_sc7_action_t * pos = clear_bw; - {size_t i; - for (i = 0; i < asizeof(clear_bw); i++) + for (size_t i = 0; i < asizeof(clear_bw); i++) { clear_bw[i].write = true; clear_bw[i].value = 0; - }} + } - {size_t i; - for (i = 0; i < arm11->brp; i++) + for (size_t i = 0; i < arm11->brp; i++) (pos++)->address = ARM11_SC7_BCR0 + i; - } - {size_t i; - for (i = 0; i < arm11->wrp; i++) + + for (size_t i = 0; i < arm11->wrp; i++) (pos++)->address = ARM11_SC7_WCR0 + i; - } + (pos++)->address = ARM11_SC7_VCR; @@ -798,17 +809,19 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value) * \param result Pointer where to store result * */ -void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result) +int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result) { arm11_run_instr_data_prepare(arm11); /* MRC p14,0,r0,c0,c5,0 (r0 = address) */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address)); /* LDC p14,c5,[R0],#4 (DTR = [r0]) */ - arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1); + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1)); arm11_run_instr_data_finish(arm11); + + return ERROR_OK; }