X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11_dbgtap.c;h=ce9acbabe25d01d98584b3629e7ad15551eec0dc;hb=133a6165728b43d74da427a0429ca56e8fb2e2cb;hp=3a50ea072327c49a7476e5b4cd38b228647fb8df;hpb=bd7d019b56a17c133f2696ae0e16f280f01236a8;p=openocd.git diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 3a50ea0723..ce9acbabe2 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (C) 2008 digenius technology GmbH. * + * Michael Bruck * * * * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com * * * @@ -24,11 +25,7 @@ #endif #include "arm11.h" -#include "jtag.h" -#include "log.h" -#include -#include #if 0 #define JTAG_DEBUG(expr ...) DEBUG(expr) @@ -36,6 +33,13 @@ #define JTAG_DEBUG(expr ...) do {} while(0) #endif +/* +This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The +behavior of the FTDI driver IIRC was to go via RTI. + +Conversely there may be other places in this code where the ARM11 code relies +on the driver to hit through RTI when coming from Update-?R. +*/ tap_state_t arm11_move_pi_to_si_via_ci[] = { TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT @@ -78,14 +82,8 @@ int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state */ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field) { - field->tap = arm11->jtag_info.tap; + field->tap = arm11->target->tap; field->num_bits = num_bits; - field->out_mask = NULL; - field->in_check_mask = NULL; - field->in_check_value = NULL; - field->in_handler = NULL; - field->in_handler_priv = NULL; - field->out_value = out_data; field->in_value = in_data; } @@ -102,7 +100,7 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) { jtag_tap_t *tap; - tap = arm11->jtag_info.tap; + tap = arm11->target->tap; if (buf_get_u32(tap->cur_instr, 0, 5) == instr) { @@ -124,19 +122,18 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) * arm11_add_debug_SCAN_N(). * */ -static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field) +static void arm11_in_handler_SCAN_N(u8 *in_value) { - /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */ + /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */ u8 v = *in_value & 0x1F; if (v != 0x10) { LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); - return ERROR_FAIL; + jtag_set_error(ERROR_FAIL); } JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); - return ERROR_OK; } /** Select and write to Scan Chain Register (SCREG) @@ -171,11 +168,14 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state) scan_field_t field; - arm11_setup_field(arm11, 5, &chain, NULL, &field); - - field.in_handler = arm11_in_handler_SCAN_N; + u8 tmp[1]; + arm11_setup_field(arm11, 5, &chain, &tmp, &field); arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state); + + jtag_execute_queue_noclear(); + + arm11_in_handler_SCAN_N(tmp); } /** Write an instruction into the ITR register @@ -212,7 +212,8 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state * same as CP14 c1 * * \param arm11 Target state variable. - * \return DSCR content + * \param value DSCR content + * \return Error status * * \remarks This is a stand-alone function that executes the JTAG command queue. */ @@ -229,11 +230,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value) arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - { - return retval; - } + CHECK_RETVAL(jtag_execute_queue()); if (arm11->last_dscr != dscr) JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr); @@ -242,7 +239,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value) *value=dscr; - return retval; + return ERROR_OK; } /** Write the Debug Status and Control Register (DSCR) @@ -266,9 +263,7 @@ int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr); @@ -383,9 +378,7 @@ int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + CHECK_RETVAL(jtag_execute_queue()); if (flag) break; @@ -446,10 +439,9 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, { Data = *data; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE)); + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry); } @@ -465,9 +457,8 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, Data = 0; arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); } @@ -486,6 +477,8 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, * layer (FT2232) that is long enough to finish execution on * the core but still shorter than any manually inducible delays. * + * To disable this code, try "memwrite burst false" + * */ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = { @@ -533,13 +526,13 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * if (count) { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); + jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE)); jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay), arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay); } else { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE); + jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE)); } } @@ -550,20 +543,17 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + CHECK_RETVAL(jtag_execute_queue()); size_t error_count = 0; - {size_t i; - for (i = 0; i < asizeof(Readies); i++) + for (size_t i = 0; i < asizeof(Readies); i++) { if (Readies[i] != 1) { error_count++; } - }} + } if (error_count) LOG_ERROR("Transfer errors " ZU, error_count); @@ -625,9 +615,8 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * dat do { arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); } @@ -707,8 +696,7 @@ int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t c arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1); arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2); - {size_t i; - for (i = 0; i < count + 1; i++) + for (size_t i = 0; i < count + 1; i++) { if (i < count) { @@ -728,9 +716,8 @@ int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t c JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW); arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready); } @@ -755,13 +742,12 @@ int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t c } } } - }} + } - {size_t i; - for (i = 0; i < count; i++) + for (size_t i = 0; i < count; i++) { JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value); - }} + } return ERROR_OK; } @@ -776,22 +762,19 @@ void arm11_sc7_clear_vbw(arm11_common_t * arm11) arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1]; arm11_sc7_action_t * pos = clear_bw; - {size_t i; - for (i = 0; i < asizeof(clear_bw); i++) + for (size_t i = 0; i < asizeof(clear_bw); i++) { clear_bw[i].write = true; clear_bw[i].value = 0; - }} + } - {size_t i; - for (i = 0; i < arm11->brp; i++) + for (size_t i = 0; i < arm11->brp; i++) (pos++)->address = ARM11_SC7_BCR0 + i; - } - {size_t i; - for (i = 0; i < arm11->wrp; i++) + + for (size_t i = 0; i < arm11->wrp; i++) (pos++)->address = ARM11_SC7_WCR0 + i; - } + (pos++)->address = ARM11_SC7_VCR; @@ -826,16 +809,13 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value) */ int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result) { - int retval; arm11_run_instr_data_prepare(arm11); /* MRC p14,0,r0,c0,c5,0 (r0 = address) */ - if ((retval=arm11_run_instr_data_to_core1(arm11, 0xee100e15, address))!=ERROR_OK) - return retval; + CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address)); /* LDC p14,c5,[R0],#4 (DTR = [r0]) */ - if ((retval=arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1))!=ERROR_OK) - return retval; + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1)); arm11_run_instr_data_finish(arm11);