X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11_dbgtap.c;h=088981f8ba882e6979f424c9c20815a0ab812ee4;hb=f06148612be714f74174bb86fe95f49df07c32fa;hp=9ad566222bf5f14a1089af963825ab6ed8d5530f;hpb=a0edb8a328ceea23186ab74c941454fb146c9a48;p=openocd.git diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 9ad566222b..088981f8ba 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -48,14 +48,14 @@ static const tap_state_t arm11_move_pi_to_si_via_ci[] = }; -static int arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields, +/* REVISIT no error handling here! */ +static void arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) { if (cmd_queue_cur_state == TAP_IRPAUSE) jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); jtag_add_ir_scan(num_fields, fields, state); - return ERROR_OK; } static const tap_state_t arm11_move_pd_to_sd_via_cd[] = @@ -63,13 +63,14 @@ static const tap_state_t arm11_move_pd_to_sd_via_cd[] = TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; -int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) +/* REVISIT no error handling here! */ +void arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, + tap_state_t state) { if (cmd_queue_cur_state == TAP_DRPAUSE) jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); jtag_add_dr_scan(num_fields, fields, state); - return ERROR_OK; } @@ -83,7 +84,8 @@ int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t * (data is written when the JTAG queue is executed) * \param field target data structure that will be initialized */ -void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field) +void arm11_setup_field(struct arm11_common *arm11, int num_bits, + void *out_data, void *in_data, struct scan_field *field) { field->tap = arm11->arm.target->tap; field->num_bits = num_bits; @@ -151,24 +153,17 @@ void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state) arm11_add_ir_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state); } -/** Verify shifted out data from Scan Chain Register (SCREG) - * Used as parameter to struct scan_field::in_handler in - * arm11_add_debug_SCAN_N(). - * - */ +/** Verify data shifted out from Scan Chain Register (SCREG). */ static void arm11_in_handler_SCAN_N(uint8_t *in_value) { - /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */ + /* Don't expect JTAG layer to modify bits we didn't ask it to read */ uint8_t v = *in_value & 0x1F; if (v != 0x10) { - LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); + LOG_ERROR("'arm11 target' JTAG error SCREG OUT 0x%02x", v); jtag_set_error(ERROR_FAIL); } - - if (v != 0x10) - JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); } /** Select and write to Scan Chain Register (SCREG) @@ -230,22 +225,23 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11, return jtag_execute_queue(); } -/** Write an instruction into the ITR register +/** + * Queue a DR scan of the ITR register. Caller must have selected + * scan chain 4 (ITR), possibly using ITRSEL. * * \param arm11 Target state variable. * \param inst An ARM11 processor instruction/opcode. - * \param flag Optional parameter to retrieve the InstCompl flag - * (this will be written when the JTAG chain is executed). - * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default - * value (Run-Test/Idle). + * \param flag Optional parameter to retrieve the Ready flag; + * this address will be written when the JTAG chain is scanned. + * \param state The TAP state to enter after the DR scan. * - * \remarks By default this ends with Run-Test/Idle state - * and causes the instruction to be executed. If - * a subsequent write to DTR is needed before - * executing the instruction then TAP_DRPAUSE should be - * passed to \p state. + * Going through the TAP_DRUPDATE state writes ITR only if Ready was + * previously set. Only the Ready flag is readable by the scan. * - * \remarks This adds to the JTAG command queue but does \em not execute it. + * An instruction loaded into ITR is executed when going through the + * TAP_IDLE state only if Ready was previously set and the debug state + * is properly set up. Depending on the instruction, you may also need + * to ensure that the rDTR is ready before that Run-Test/Idle state. */ static void arm11_add_debug_INST(struct arm11_common * arm11, uint32_t inst, uint8_t * flag, tap_state_t state) @@ -257,7 +253,7 @@ static void arm11_add_debug_INST(struct arm11_common * arm11, arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); arm11_setup_field(arm11, 1, NULL, flag, itr + 1); - arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state); + arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state); } /** @@ -374,7 +370,11 @@ int arm11_run_instr_data_finish(struct arm11_common * arm11) -/** Execute one or multiple instructions via ITR +/** + * Execute one or more instructions via ITR. + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block * @@ -444,6 +444,10 @@ int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode) /** Execute one instruction via ITR repeatedly while * passing data to the core via DTR on each execution. * + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. + * * The executed instruction \em must read data from DTR. * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block @@ -570,6 +574,10 @@ static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = /** Execute one instruction via ITR repeatedly while * passing data to the core via DTR on each execution. * + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. + * * No Ready check during transmission. * * The executed instruction \em must read data from DTR. @@ -678,6 +686,10 @@ int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, /** Execute one instruction via ITR repeatedly while * reading data from the core via DTR on each execution. * + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. + * * The executed instruction \em must write data to DTR. * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block