X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11.h;h=c3f4e8643bfa6fc6aab38551f869734cd6b484d0;hb=e232dea176cc8c831e77a10903120ff057337f6c;hp=9bc6eb44e4fed57624654cbb73a7d90bbaceeec7;hpb=2280ddeea5fd82554696f1caa97f7a485a035da4;p=openocd.git

diff --git a/src/target/arm11.h b/src/target/arm11.h
index 9bc6eb44e4..c3f4e8643b 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -24,49 +24,21 @@
 #define ARM11_H
 
 #include "armv4_5.h"
+#include "arm_dpm.h"
 
-#define asizeof(x)	(sizeof(x) / sizeof((x)[0]))
-
-#define NEW(type, variable, items)			\
-	type * variable = calloc(1, sizeof(type) * items)
-
-/* For MinGW use 'I' prefix to print size_t (instead of 'z') */
-/* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW    */
-
-#if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO))
-#define ZU		"%zu"
-#else
-#define ZU		"%Iu"
-#endif
-
-#define ARM11_REGCACHE_MODEREGS		0
-#define ARM11_REGCACHE_FREGS		0
-
-#define ARM11_REGCACHE_COUNT		(20 +					\
-					 23 * ARM11_REGCACHE_MODEREGS +			\
-					  9 * ARM11_REGCACHE_FREGS)
+#define ARM11_REGCACHE_COUNT		3
 
 #define ARM11_TAP_DEFAULT			TAP_INVALID
 
-
-#define CHECK_RETVAL(action)								\
-do {														\
-	int __retval = (action);								\
-															\
-	if (__retval != ERROR_OK)								\
-	{														\
-		LOG_DEBUG("error while calling \"" # action "\"");	\
-		return __retval;									\
-	}														\
-															\
-} while (0)
-
-
-struct arm11_register_history
-{
-	uint32_t		value;
-	uint8_t		valid;
-};
+#define CHECK_RETVAL(action)			\
+	do {					\
+		int __retval = (action);	\
+		if (__retval != ERROR_OK) {	\
+			LOG_DEBUG("error while calling \"%s\"",	\
+				# action );	\
+			return __retval;	\
+		}				\
+	} while (0)
 
 enum arm11_debug_version
 {
@@ -81,18 +53,15 @@ struct arm11_common
 	struct arm	arm;
 	struct target *	target;		/**< Reference back to the owner */
 
+	/** Debug module state. */
+	struct arm_dpm dpm;
+
 	/** \name Processor type detection */
 	/*@{*/
 
-	uint32_t		device_id;		/**< IDCODE readout				*/
-	uint32_t		didr;			/**< DIDR readout (debug capabilities)	*/
-	uint8_t		implementor;	/**< DIDR Implementor readout		*/
-
 	size_t	brp;			/**< Number of Breakpoint Register Pairs from DIDR	*/
 	size_t	wrp;			/**< Number of Watchpoint Register Pairs from DIDR	*/
 
-	enum arm11_debug_version
-		debug_version;		/**< ARM debug architecture from DIDR	*/
 	/*@}*/
 
 	uint32_t		last_dscr;		/**< Last retrieved DSCR value;
@@ -100,7 +69,7 @@ struct arm11_common
 
 	bool	simulate_reset_on_next_halt;	/**< Perform cleanups of the ARM state on next halt */
 
-	/** \name Shadow registers to save processor state */
+	/** \name Shadow registers to save debug state */
 	/*@{*/
 
 	struct reg *	reg_list;							/**< target register list */
@@ -108,9 +77,6 @@ struct arm11_common
 
 	/*@}*/
 
-	struct arm11_register_history
-		reg_history[ARM11_REGCACHE_COUNT];	/**< register state before last resume */
-
 	size_t	free_brps;				/**< keep track of breakpoints allocated by arm11_add_breakpoint() */
 	size_t	free_wrps;				/**< keep track of breakpoints allocated by arm11_add_watchpoint() */