X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11.h;h=9edadee1d911681f4f7b80c5305e0223b32c321f;hb=e03f45f6996ca9b646c228cad8431dea73054818;hp=5f78db5dfab966b81cf5782edff0d0081291b1f9;hpb=6eee0729d79eab496d1d4368a2bae7e4e2d19876;p=openocd.git diff --git a/src/target/arm11.h b/src/target/arm11.h index 5f78db5dfa..9edadee1d9 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -23,8 +23,8 @@ #ifndef ARM11_H #define ARM11_H -#include -#include +#include "arm.h" +#include "arm_dpm.h" #define ARM11_TAP_DEFAULT TAP_INVALID @@ -53,9 +53,10 @@ struct arm11_common /** Debug module state. */ struct arm_dpm dpm; + struct arm11_sc7_action *bpwp_actions; + unsigned bpwp_n; size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ - size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */ size_t free_brps; /**< Number of breakpoints allocated */ uint32_t dscr; /**< Last retrieved DSCR value. */ @@ -68,6 +69,18 @@ struct arm11_common bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ + /* Per-core configurable options. + * NOTE that several of these boolean options should not exist + * once the relevant code is known to work correctly. + */ + bool memwrite_burst; + bool memwrite_error_fatal; + bool step_irq_enable; + bool hardware_step; + + /** Configured Vector Catch Register settings. */ + uint32_t vcr; + struct arm_jtag jtag_info; }; @@ -94,18 +107,6 @@ enum arm11_instructions ARM11_BYPASS = 0x1F, }; -enum arm11_dscr -{ - - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2, -}; - enum arm11_sc7 { ARM11_SC7_NULL = 0,