X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=e9ba1f678d6645862b87fa08cc0a4d69f3d3c714;hb=177bbd8891ae737ea7f8c0791a6236f72cedee40;hp=890b836bb29015916feff62da9db80d676b029f1;hpb=e6dac739cffdecc0c65254eb7b3f2942cfff0f68;p=openocd.git diff --git a/src/target/arm11.c b/src/target/arm11.c index 890b836bb2..30dbedb939 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -1,5 +1,10 @@ /*************************************************************************** * Copyright (C) 2008 digenius technology GmbH. * + * Michael Bruck * + * * + * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com * + * * + * Copyright (C) 2008 Georg Acher * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -21,341 +26,126 @@ #include "config.h" #endif -#include "arm11.h" -#include "jtag.h" -#include "log.h" +#include "etm.h" +#include "breakpoints.h" +#include "arm11_dbgtap.h" +#include "arm_simulator.h" +#include "time_support.h" +#include "target_type.h" +#include "algorithm.h" +#include "register.h" -#include -#include #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif - -#if 0 -#define FNC_INFO DEBUG("-") -#else -#define FNC_INFO -#endif - -#if 1 -#define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0) -#else -#define FNC_INFO_NOTIMPLEMENTED -#endif - -static void arm11_on_enter_debug_state(arm11_common_t * arm11); - - -bool arm11_config_memwrite_burst = true; -bool arm11_config_memwrite_error_fatal = true; -u32 arm11_vcr = 0; - - -#define ARM11_HANDLER(x) \ - .x = arm11_##x - -target_type_t arm11_target = -{ - .name = "arm11", - - ARM11_HANDLER(poll), - ARM11_HANDLER(arch_state), - - ARM11_HANDLER(target_request_data), - - ARM11_HANDLER(halt), - ARM11_HANDLER(resume), - ARM11_HANDLER(step), - - ARM11_HANDLER(assert_reset), - ARM11_HANDLER(deassert_reset), - ARM11_HANDLER(soft_reset_halt), - ARM11_HANDLER(prepare_reset_halt), - - ARM11_HANDLER(get_gdb_reg_list), - - ARM11_HANDLER(read_memory), - ARM11_HANDLER(write_memory), - - ARM11_HANDLER(bulk_write_memory), - - ARM11_HANDLER(checksum_memory), - - ARM11_HANDLER(add_breakpoint), - ARM11_HANDLER(remove_breakpoint), - ARM11_HANDLER(add_watchpoint), - ARM11_HANDLER(remove_watchpoint), - - ARM11_HANDLER(run_algorithm), - - ARM11_HANDLER(register_commands), - ARM11_HANDLER(target_command), - ARM11_HANDLER(init_target), - ARM11_HANDLER(quit), -}; - -int arm11_regs_arch_type = -1; - +static bool arm11_config_memwrite_burst = true; +static bool arm11_config_memwrite_error_fatal = true; +static uint32_t arm11_vcr = 0; +static bool arm11_config_step_irq_enable = false; +static bool arm11_config_hardware_step = false; enum arm11_regtype { - ARM11_REGISTER_CORE, - ARM11_REGISTER_CPSR, - - ARM11_REGISTER_FX, - ARM11_REGISTER_FPS, - - ARM11_REGISTER_FIQ, - ARM11_REGISTER_SVC, - ARM11_REGISTER_ABT, - ARM11_REGISTER_IRQ, - ARM11_REGISTER_UND, - ARM11_REGISTER_MON, - - ARM11_REGISTER_SPSR_FIQ, - ARM11_REGISTER_SPSR_SVC, - ARM11_REGISTER_SPSR_ABT, - ARM11_REGISTER_SPSR_IRQ, - ARM11_REGISTER_SPSR_UND, - ARM11_REGISTER_SPSR_MON, - - /* debug regs */ - ARM11_REGISTER_DSCR, - ARM11_REGISTER_WDTR, - ARM11_REGISTER_RDTR, + /* debug regs */ + ARM11_REGISTER_DSCR, + ARM11_REGISTER_WDTR, + ARM11_REGISTER_RDTR, }; -typedef struct arm11_reg_defs_s +struct arm11_reg_defs { - char * name; - u32 num; - int gdb_num; - enum arm11_regtype type; -} arm11_reg_defs_t; + char * name; + uint32_t num; + int gdb_num; + enum arm11_regtype type; +}; /* update arm11_regcache_ids when changing this */ -static const arm11_reg_defs_t arm11_reg_defs[] = +static const struct arm11_reg_defs arm11_reg_defs[] = { - {"r0", 0, 0, ARM11_REGISTER_CORE}, - {"r1", 1, 1, ARM11_REGISTER_CORE}, - {"r2", 2, 2, ARM11_REGISTER_CORE}, - {"r3", 3, 3, ARM11_REGISTER_CORE}, - {"r4", 4, 4, ARM11_REGISTER_CORE}, - {"r5", 5, 5, ARM11_REGISTER_CORE}, - {"r6", 6, 6, ARM11_REGISTER_CORE}, - {"r7", 7, 7, ARM11_REGISTER_CORE}, - {"r8", 8, 8, ARM11_REGISTER_CORE}, - {"r9", 9, 9, ARM11_REGISTER_CORE}, - {"r10", 10, 10, ARM11_REGISTER_CORE}, - {"r11", 11, 11, ARM11_REGISTER_CORE}, - {"r12", 12, 12, ARM11_REGISTER_CORE}, - {"sp", 13, 13, ARM11_REGISTER_CORE}, - {"lr", 14, 14, ARM11_REGISTER_CORE}, - {"pc", 15, 15, ARM11_REGISTER_CORE}, - -#if ARM11_REGCACHE_FREGS - {"f0", 0, 16, ARM11_REGISTER_FX}, - {"f1", 1, 17, ARM11_REGISTER_FX}, - {"f2", 2, 18, ARM11_REGISTER_FX}, - {"f3", 3, 19, ARM11_REGISTER_FX}, - {"f4", 4, 20, ARM11_REGISTER_FX}, - {"f5", 5, 21, ARM11_REGISTER_FX}, - {"f6", 6, 22, ARM11_REGISTER_FX}, - {"f7", 7, 23, ARM11_REGISTER_FX}, - {"fps", 0, 24, ARM11_REGISTER_FPS}, -#endif - - {"cpsr", 0, 25, ARM11_REGISTER_CPSR}, - -#if ARM11_REGCACHE_MODEREGS - {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ}, - {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ}, - {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ}, - {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ}, - {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ}, - {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ}, - {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ}, - {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ}, - - {"r13_svc", 13, -1, ARM11_REGISTER_SVC}, - {"r14_svc", 14, -1, ARM11_REGISTER_SVC}, - {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC}, - - {"r13_abt", 13, -1, ARM11_REGISTER_ABT}, - {"r14_abt", 14, -1, ARM11_REGISTER_ABT}, - {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT}, - - {"r13_irq", 13, -1, ARM11_REGISTER_IRQ}, - {"r14_irq", 14, -1, ARM11_REGISTER_IRQ}, - {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ}, - - {"r13_und", 13, -1, ARM11_REGISTER_UND}, - {"r14_und", 14, -1, ARM11_REGISTER_UND}, - {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND}, - - /* ARM1176 only */ - {"r13_mon", 13, -1, ARM11_REGISTER_MON}, - {"r14_mon", 14, -1, ARM11_REGISTER_MON}, - {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON}, -#endif - - /* Debug Registers */ - {"dscr", 0, -1, ARM11_REGISTER_DSCR}, - {"wdtr", 0, -1, ARM11_REGISTER_WDTR}, - {"rdtr", 0, -1, ARM11_REGISTER_RDTR}, + /* Debug Registers */ + {"dscr", 0, -1, ARM11_REGISTER_DSCR}, + {"wdtr", 0, -1, ARM11_REGISTER_WDTR}, + {"rdtr", 0, -1, ARM11_REGISTER_RDTR}, }; enum arm11_regcache_ids { - ARM11_RC_R0, - ARM11_RC_RX = ARM11_RC_R0, - - ARM11_RC_R1, - ARM11_RC_R2, - ARM11_RC_R3, - ARM11_RC_R4, - ARM11_RC_R5, - ARM11_RC_R6, - ARM11_RC_R7, - ARM11_RC_R8, - ARM11_RC_R9, - ARM11_RC_R10, - ARM11_RC_R11, - ARM11_RC_R12, - ARM11_RC_R13, - ARM11_RC_SP = ARM11_RC_R13, - ARM11_RC_R14, - ARM11_RC_LR = ARM11_RC_R14, - ARM11_RC_R15, - ARM11_RC_PC = ARM11_RC_R15, - -#if ARM11_REGCACHE_FREGS - ARM11_RC_F0, - ARM11_RC_FX = ARM11_RC_F0, - ARM11_RC_F1, - ARM11_RC_F2, - ARM11_RC_F3, - ARM11_RC_F4, - ARM11_RC_F5, - ARM11_RC_F6, - ARM11_RC_F7, - ARM11_RC_FPS, -#endif - - ARM11_RC_CPSR, - -#if ARM11_REGCACHE_MODEREGS - ARM11_RC_R8_FIQ, - ARM11_RC_R9_FIQ, - ARM11_RC_R10_FIQ, - ARM11_RC_R11_FIQ, - ARM11_RC_R12_FIQ, - ARM11_RC_R13_FIQ, - ARM11_RC_R14_FIQ, - ARM11_RC_SPSR_FIQ, - - ARM11_RC_R13_SVC, - ARM11_RC_R14_SVC, - ARM11_RC_SPSR_SVC, - - ARM11_RC_R13_ABT, - ARM11_RC_R14_ABT, - ARM11_RC_SPSR_ABT, - - ARM11_RC_R13_IRQ, - ARM11_RC_R14_IRQ, - ARM11_RC_SPSR_IRQ, - - ARM11_RC_R13_UND, - ARM11_RC_R14_UND, - ARM11_RC_SPSR_UND, - - ARM11_RC_R13_MON, - ARM11_RC_R14_MON, - ARM11_RC_SPSR_MON, -#endif - - ARM11_RC_DSCR, - ARM11_RC_WDTR, - ARM11_RC_RDTR, - - ARM11_RC_MAX, -}; - -#define ARM11_GDB_REGISTER_COUNT 26 - -u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -reg_t arm11_gdb_dummy_fp_reg = -{ - "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 -}; + ARM11_RC_DSCR, + ARM11_RC_WDTR, + ARM11_RC_RDTR, -u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0}; - -reg_t arm11_gdb_dummy_fps_reg = -{ - "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 + ARM11_RC_MAX, }; +static int arm11_on_enter_debug_state(struct arm11_common *arm11); +static int arm11_step(struct target *target, int current, + uint32_t address, int handle_breakpoints); +/* helpers */ +static int arm11_build_reg_cache(struct target *target); +static int arm11_set_reg(struct reg *reg, uint8_t *buf); +static int arm11_get_reg(struct reg *reg); /** Check and if necessary take control of the system * * \param arm11 Target state variable. * \param dscr If the current DSCR content is - * available a pointer to a word holding the - * DSCR can be passed. Otherwise use NULL. + * available a pointer to a word holding the + * DSCR can be passed. Otherwise use NULL. */ -void arm11_check_init(arm11_common_t * arm11, u32 * dscr) +static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr) { - FNC_INFO; + uint32_t dscr_local_tmp_copy; + + if (!dscr) + { + dscr = &dscr_local_tmp_copy; - u32 dscr_local_tmp_copy; + CHECK_RETVAL(arm11_read_DSCR(arm11, dscr)); + } - if (!dscr) - { - dscr = &dscr_local_tmp_copy; - *dscr = arm11_read_DSCR(arm11); - } + if (!(*dscr & ARM11_DSCR_MODE_SELECT)) + { + LOG_DEBUG("Bringing target into debug mode"); - if (!(*dscr & ARM11_DSCR_MODE_SELECT)) - { - DEBUG("Bringing target into debug mode"); + *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */ + arm11_write_DSCR(arm11, *dscr); - *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */ - arm11_write_DSCR(arm11, *dscr); + /* add further reset initialization here */ - /* add further reset initialization here */ + arm11->simulate_reset_on_next_halt = true; - arm11->simulate_reset_on_next_halt = true; + if (*dscr & ARM11_DSCR_CORE_HALTED) + { + /** \todo TODO: this needs further scrutiny because + * arm11_on_enter_debug_state() never gets properly called. + * As a result we don't read the actual register states from + * the target. + */ - if (*dscr & ARM11_DSCR_CORE_HALTED) - { - /** \todo TODO: this needs further scrutiny because - * arm11_on_enter_debug_state() never gets properly called - */ + arm11->target->state = TARGET_HALTED; + arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr); + } + else + { + arm11->target->state = TARGET_RUNNING; + arm11->target->debug_reason = DBG_REASON_NOTHALTED; + } - arm11->target->state = TARGET_HALTED; - arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr); - } - else - { - arm11->target->state = TARGET_RUNNING; - arm11->target->debug_reason = DBG_REASON_NOTHALTED; + arm11_sc7_clear_vbw(arm11); } - arm11_sc7_clear_vbw(arm11); - } + return ERROR_OK; } #define R(x) \ - (arm11->reg_values[ARM11_RC_##x]) + (arm11->reg_values[ARM11_RC_##x]) /** Save processor state. * @@ -363,1431 +153,1540 @@ void arm11_check_init(arm11_common_t * arm11, u32 * dscr) * or on other occasions that stop the processor. * */ -static void arm11_on_enter_debug_state(arm11_common_t * arm11) +static int arm11_on_enter_debug_state(struct arm11_common *arm11) { - FNC_INFO; + int retval; - {size_t i; - for(i = 0; i < asizeof(arm11->reg_values); i++) - { - arm11->reg_list[i].valid = 1; - arm11->reg_list[i].dirty = 0; - }} + /* REVISIT entire cache should already be invalid !!! */ + register_cache_invalidate(arm11->arm.core_cache); - /* Save DSCR */ + for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++) + { + arm11->reg_list[i].valid = 1; + arm11->reg_list[i].dirty = 0; + } - R(DSCR) = arm11_read_DSCR(arm11); + /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */ - /* Save wDTR */ + /* Save DSCR */ + CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR))); - if (R(DSCR) & ARM11_DSCR_WDTR_FULL) - { - arm11_add_debug_SCAN_N(arm11, 0x05, -1); + /* Save wDTR */ - arm11_add_IR(arm11, ARM11_INTEST, -1); + if (R(DSCR) & ARM11_DSCR_WDTR_FULL) + { + arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0); - arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); - arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); + struct scan_field chain5_fields[3]; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); - } - else - { - arm11->reg_list[ARM11_RC_WDTR].valid = 0; - } + arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0); + arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); + arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); + } + else + { + arm11->reg_list[ARM11_RC_WDTR].valid = 0; + } - /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */ - /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs - ARM1136 seems to require this to issue ITR's as well */ - u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE; + /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE + * + * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", + * but not to issue ITRs. ARM1136 seems to require this to issue + * ITR's as well... + */ + uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE; - /* this executes JTAG queue: */ + /* this executes JTAG queue: */ - arm11_write_DSCR(arm11, new_dscr); + arm11_write_DSCR(arm11, new_dscr); - /* From the spec: - Before executing any instruction in debug state you have to drain the write buffer. - This ensures that no imprecise Data Aborts can return at a later point:*/ + /* From the spec: + Before executing any instruction in debug state you have to drain the write buffer. + This ensures that no imprecise Data Aborts can return at a later point:*/ - /** \todo TODO: Test drain write buffer. */ + /** \todo TODO: Test drain write buffer. */ #if 0 - while (1) - { - /* MRC p14,0,R0,c5,c10,0 */ -// arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000); - - /* mcr 15, 0, r0, cr7, cr10, {4} */ - arm11_run_instr_no_data1(arm11, 0xee070f9a); - - u32 dscr = arm11_read_DSCR(arm11); - - DEBUG("DRAIN, DSCR %08x", dscr); - - if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) + while (1) { - arm11_run_instr_no_data1(arm11, 0xe320f000); - - dscr = arm11_read_DSCR(arm11); - - DEBUG("DRAIN, DSCR %08x (DONE)", dscr); - - break; - } - } -#endif - - - arm11_run_instr_data_prepare(arm11); + /* MRC p14,0,R0,c5,c10,0 */ + // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000); - /* save r0 - r14 */ + /* mcr 15, 0, r0, cr7, cr10, {4} */ + arm11_run_instr_no_data1(arm11, 0xee070f9a); + uint32_t dscr = arm11_read_DSCR(arm11); - /** \todo TODO: handle other mode registers */ + LOG_DEBUG("DRAIN, DSCR %08x", dscr); - {size_t i; - for (i = 0; i < 15; i++) - { - /* MCR p14,0,R?,c0,c5,0 */ - arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1); - }} + if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) + { + arm11_run_instr_no_data1(arm11, 0xe320f000); + dscr = arm11_read_DSCR(arm11); - /* save rDTR */ + LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr); - /* check rDTRfull in DSCR */ - - if (R(DSCR) & ARM11_DSCR_RDTR_FULL) - { - /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */ - arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR)); - } - else - { - arm11->reg_list[ARM11_RC_RDTR].valid = 0; - } - - /* save CPSR */ + break; + } + } +#endif - /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */ - arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR)); + /* Save registers. + * + * NOTE: ARM1136 TRM suggests saving just R0 here now, then + * CPSR and PC after the rDTR stuff. We do it all at once. + */ + retval = arm_dpm_read_current_registers(&arm11->dpm); + if (retval != ERROR_OK) + LOG_ERROR("DPM REG READ -- fail %d", retval); - /* save PC */ + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; - /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */ - arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC)); + /* maybe save rDTR */ - /* adjust PC depending on ARM state */ + /* check rDTRfull in DSCR */ - if (R(CPSR) & ARM11_CPSR_J) /* Java state */ - { - arm11->reg_values[ARM11_RC_PC] -= 0; - } - else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */ - { - arm11->reg_values[ARM11_RC_PC] -= 4; - } - else /* ARM state */ - { - arm11->reg_values[ARM11_RC_PC] -= 8; - } + if (R(DSCR) & ARM11_DSCR_RDTR_FULL) + { + /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */ + retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR)); + if (retval != ERROR_OK) + return retval; + } + else + { + arm11->reg_list[ARM11_RC_RDTR].valid = 0; + } - if (arm11->simulate_reset_on_next_halt) - { - arm11->simulate_reset_on_next_halt = false; + /* REVISIT Now that we've saved core state, there's may also + * be MMU and cache state to care about ... + */ - DEBUG("Reset c1 Control Register"); + if (arm11->simulate_reset_on_next_halt) + { + arm11->simulate_reset_on_next_halt = false; - /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */ + LOG_DEBUG("Reset c1 Control Register"); - /* MCR p15,0,R0,c1,c0,0 */ - arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0); + /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */ - } + /* MCR p15,0,R0,c1,c0,0 */ + retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0); + if (retval != ERROR_OK) + return retval; - arm11_run_instr_data_finish(arm11); + } - arm11_dump_reg_changes(arm11); -} + retval = arm11_run_instr_data_finish(arm11); + if (retval != ERROR_OK) + return retval; -void arm11_dump_reg_changes(arm11_common_t * arm11) -{ - {size_t i; - for(i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - if (!arm11->reg_list[i].valid) - { - if (arm11->reg_history[i].valid) - INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value); - } - else - { - if (arm11->reg_history[i].valid) - { - if (arm11->reg_history[i].value != arm11->reg_values[i]) - INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value); - } - else - { - INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]); - } - } - }} + return ERROR_OK; } - /** Restore processor state * * This is called in preparation for the RESTART function. * */ -void arm11_leave_debug_state(arm11_common_t * arm11) +static int arm11_leave_debug_state(struct arm11_common *arm11) { - FNC_INFO; - - arm11_run_instr_data_prepare(arm11); + int retval; - /** \todo TODO: handle other mode registers */ + /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */ - /* restore R1 - R14 */ - {size_t i; - for (i = 1; i < 15; i++) - { - if (!arm11->reg_list[ARM11_RC_RX + i].dirty) - continue; + /* NOTE: the ARM1136 TRM suggests restoring all registers + * except R0/PC/CPSR right now. Instead, we do them all + * at once, just a bit later on. + */ - /* MRC p14,0,r?,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i)); + /* REVISIT once we start caring about MMU and cache state, + * address it here ... + */ -// DEBUG("RESTORE R" ZU " %08x", i, R(RX + i)); - }} - - arm11_run_instr_data_finish(arm11); - - - /* spec says clear wDTR and rDTR; we assume they are clear as - otherwise our programming would be sloppy */ - - { - u32 DSCR = arm11_read_DSCR(arm11); - - if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL)) + /* spec says clear wDTR and rDTR; we assume they are clear as + otherwise our programming would be sloppy */ { - ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR); + uint32_t DSCR; + + CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR)); + + if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL)) + { + /* + The wDTR/rDTR two registers that are used to send/receive data to/from + the core in tandem with corresponding instruction codes that are + written into the core. The RDTR FULL/WDTR FULL flag indicates that the + registers hold data that was written by one side (CPU or JTAG) and not + read out by the other side. + */ + LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR); + return ERROR_FAIL; + } } - } - - arm11_run_instr_data_prepare(arm11); - - /* restore original wDTR */ - - if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty) - { - /* MCR p14,0,R0,c0,c5,0 */ - arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR)); - } - - /* restore CPSR */ - - /* MSR CPSR,R0*/ - arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR)); - - /* restore PC */ - - /* MOV PC,R0 */ - arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC)); - - - /* restore R0 */ - - /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0)); + /* maybe restore original wDTR */ + if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty) + { + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; + + /* MCR p14,0,R0,c0,c5,0 */ + retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR)); + if (retval != ERROR_OK) + return retval; + + retval = arm11_run_instr_data_finish(arm11); + if (retval != ERROR_OK) + return retval; + } - arm11_run_instr_data_finish(arm11); + /* restore CPSR, PC, and R0 ... after flushing any modified + * registers. + */ + retval = arm_dpm_write_dirty_registers(&arm11->dpm); + register_cache_invalidate(arm11->arm.core_cache); - /* restore DSCR */ + /* restore DSCR */ - arm11_write_DSCR(arm11, R(DSCR)); + arm11_write_DSCR(arm11, R(DSCR)); + /* maybe restore rDTR */ - /* restore rDTR */ - - if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty) - { - arm11_add_debug_SCAN_N(arm11, 0x05, -1); + if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty) + { + arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); - arm11_add_IR(arm11, ARM11_EXTEST, -1); + arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; - u8 Ready = 0; /* ignored */ - u8 Valid = 0; /* ignored */ + uint8_t Ready = 0; /* ignored */ + uint8_t Valid = 0; /* ignored */ - arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0); - arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); - arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); + arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0); + arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); + arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); - } + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); + } - arm11_record_register_history(arm11); -} + /* now processor is ready to RESTART */ -void arm11_record_register_history(arm11_common_t * arm11) -{ - {size_t i; - for(i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - arm11->reg_history[i].value = arm11->reg_values[i]; - arm11->reg_history[i].valid = arm11->reg_list[i].valid; - - arm11->reg_list[i].valid = 0; - arm11->reg_list[i].dirty = 0; - }} + return ERROR_OK; } - /* poll current target status */ -int arm11_poll(struct target_s *target) +static int arm11_poll(struct target *target) { - FNC_INFO; + int retval; + struct arm11_common *arm11 = target_to_arm11(target); + uint32_t dscr; - arm11_common_t * arm11 = target->arch_info; + CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); - if (arm11->trst_active) - return ERROR_OK; - - u32 dscr = arm11_read_DSCR(arm11); - - DEBUG("DSCR %08x", dscr); + LOG_DEBUG("DSCR %08" PRIx32 "", dscr); - arm11_check_init(arm11, &dscr); + CHECK_RETVAL(arm11_check_init(arm11, &dscr)); - if (dscr & ARM11_DSCR_CORE_HALTED) - { - if (target->state != TARGET_HALTED) + if (dscr & ARM11_DSCR_CORE_HALTED) { - enum target_state old_state = target->state; - - DEBUG("enter TARGET_HALTED"); - target->state = TARGET_HALTED; - target->debug_reason = arm11_get_DSCR_debug_reason(dscr); - arm11_on_enter_debug_state(arm11); - - target_call_event_callbacks(target, - old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED); + if (target->state != TARGET_HALTED) + { + enum target_state old_state = target->state; + + LOG_DEBUG("enter TARGET_HALTED"); + target->state = TARGET_HALTED; + target->debug_reason = arm11_get_DSCR_debug_reason(dscr); + retval = arm11_on_enter_debug_state(arm11); + if (retval != ERROR_OK) + return retval; + + target_call_event_callbacks(target, + old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED); + } } - } - else - { - if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) + else { - DEBUG("enter TARGET_RUNNING"); - target->state = TARGET_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; + if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) + { + LOG_DEBUG("enter TARGET_RUNNING"); + target->state = TARGET_RUNNING; + target->debug_reason = DBG_REASON_NOTHALTED; + } } - } - return ERROR_OK; + return ERROR_OK; } /* architecture specific status reply */ -int arm11_arch_state(struct target_s *target) +static int arm11_arch_state(struct target *target) { - FNC_INFO_NOTIMPLEMENTED; + int retval; - return ERROR_OK; -} + retval = armv4_5_arch_state(target); + + /* REVISIT also display ARM11-specific MMU and cache status ... */ + return retval; +} /* target request support */ -int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer) +static int arm11_target_request_data(struct target *target, + uint32_t size, uint8_t *buffer) { - FNC_INFO_NOTIMPLEMENTED; + LOG_WARNING("Not implemented: %s", __func__); - return ERROR_OK; + return ERROR_FAIL; } - - /* target execution control */ -int arm11_halt(struct target_s *target) +static int arm11_halt(struct target *target) { - FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); - DEBUG("target->state: %s", target_state_strings[target->state]); - - if (target->state == TARGET_UNKNOWN) - { - arm11->simulate_reset_on_next_halt = true; - } - - if (target->state == TARGET_HALTED) - { - WARNING("target was already halted"); - return ERROR_OK; - } + LOG_DEBUG("target->state: %s", + target_state_name(target)); - if (arm11->trst_active) - { - arm11->halt_requested = true; - return ERROR_OK; - } + if (target->state == TARGET_UNKNOWN) + { + arm11->simulate_reset_on_next_halt = true; + } - arm11_add_IR(arm11, ARM11_HALT, TAP_RTI); + if (target->state == TARGET_HALTED) + { + LOG_DEBUG("target was already halted"); + return ERROR_OK; + } - jtag_execute_queue(); + arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE); - u32 dscr; + CHECK_RETVAL(jtag_execute_queue()); - while (1) - { - dscr = arm11_read_DSCR(arm11); + uint32_t dscr; - if (dscr & ARM11_DSCR_CORE_HALTED) - break; - } + int i = 0; + while (1) + { + CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); + + if (dscr & ARM11_DSCR_CORE_HALTED) + break; + + + long long then = 0; + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + i++; + } - arm11_on_enter_debug_state(arm11); + arm11_on_enter_debug_state(arm11); - enum target_state old_state = target->state; + enum target_state old_state = target->state; - target->state = TARGET_HALTED; - target->debug_reason = arm11_get_DSCR_debug_reason(dscr); + target->state = TARGET_HALTED; + target->debug_reason = arm11_get_DSCR_debug_reason(dscr); - target_call_event_callbacks(target, - old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED); + CHECK_RETVAL( + target_call_event_callbacks(target, + old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)); - return ERROR_OK; + return ERROR_OK; } - -int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) +static uint32_t +arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address) { - FNC_INFO; + void *value = arm11->arm.core_cache->reg_list[15].value; -// DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", -// current, address, handle_breakpoints, debug_execution); - - arm11_common_t * arm11 = target->arch_info; - - DEBUG("target->state: %s", target_state_strings[target->state]); - - if (target->state != TARGET_HALTED) - { - WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - if (!current) - R(PC) = address; - - INFO("RESUME PC %08x%s", R(PC), !current ? "!" : ""); + if (!current) + buf_set_u32(value, 0, 32, address); + else + address = buf_get_u32(value, 0, 32); - /* clear breakpoints/watchpoints and VCR*/ - arm11_sc7_clear_vbw(arm11); + return address; +} - /* Set up breakpoints */ - if (!debug_execution) - { - /* check if one matches PC and step over it if necessary */ +static int arm11_resume(struct target *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) +{ + // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", + // current, address, handle_breakpoints, debug_execution); - breakpoint_t * bp; + struct arm11_common *arm11 = target_to_arm11(target); - for (bp = target->breakpoints; bp; bp = bp->next) - { - if (bp->address == R(PC)) - { - DEBUG("must step over %08x", bp->address); - arm11_step(target, 1, 0, 0); - break; - } - } + LOG_DEBUG("target->state: %s", + target_state_name(target)); - /* set all breakpoints */ - size_t brp_num = 0; - - for (bp = target->breakpoints; bp; bp = bp->next) + if (target->state != TARGET_HALTED) { - arm11_sc7_action_t brp[2]; - - brp[0].write = 1; - brp[0].address = ARM11_SC7_BVR0 + brp_num; - brp[0].value = bp->address; - brp[1].write = 1; - brp[1].address = ARM11_SC7_BCR0 + brp_num; - brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); - - arm11_sc7_run(arm11, brp, asizeof(brp)); - - DEBUG("Add BP " ZU " at %08x", brp_num, bp->address); - - brp_num++; + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; } - arm11_sc7_set_vcr(arm11, arm11_vcr); - } - - - arm11_leave_debug_state(arm11); - - arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI); + address = arm11_nextpc(arm11, current, address); - jtag_execute_queue(); + LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : ""); - while (1) - { - u32 dscr = arm11_read_DSCR(arm11); - - DEBUG("DSCR %08x", dscr); - - if (dscr & ARM11_DSCR_CORE_RESTARTED) - break; - } - - if (!debug_execution) - { - target->state = TARGET_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; - target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - } - else - { - target->state = TARGET_DEBUG_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; - target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); - } - - return ERROR_OK; -} - -int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints) -{ - FNC_INFO; - - DEBUG("target->state: %s", target_state_strings[target->state]); - - if (target->state != TARGET_HALTED) - { - WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - arm11_common_t * arm11 = target->arch_info; - - if (!current) - R(PC) = address; + /* clear breakpoints/watchpoints and VCR*/ + arm11_sc7_clear_vbw(arm11); - INFO("STEP PC %08x%s", R(PC), !current ? "!" : ""); + if (!debug_execution) + target_free_all_working_areas(target); - /** \todo TODO: Thumb not supported here */ + /* Set up breakpoints */ + if (handle_breakpoints) + { + /* check if one matches PC and step over it if necessary */ - u32 next_instruction; + struct breakpoint * bp; - arm11_read_memory_word(arm11, R(PC), &next_instruction); + for (bp = target->breakpoints; bp; bp = bp->next) + { + if (bp->address == address) + { + LOG_DEBUG("must step over %08" PRIx32 "", bp->address); + arm11_step(target, 1, 0, 0); + break; + } + } - /* skip over BKPT */ - if ((next_instruction & 0xFFF00070) == 0xe1200070) - { - R(PC) += 4; - arm11->reg_list[ARM11_RC_PC].valid = 1; - arm11->reg_list[ARM11_RC_PC].dirty = 0; - INFO("Skipping BKPT"); - } - /* skip over Wait for interrupt / Standby */ - /* mcr 15, 0, r?, cr7, cr0, {4} */ - else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) - { - R(PC) += 4; - arm11->reg_list[ARM11_RC_PC].valid = 1; - arm11->reg_list[ARM11_RC_PC].dirty = 0; - INFO("Skipping WFI"); - } - /* ignore B to self */ - else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe) - { - INFO("Not stepping jump to self"); - } - else - { - /** \todo TODO: check if break-/watchpoints make any sense at all in combination - * with this. */ + /* set all breakpoints */ - /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively - * the VCR might be something worth looking into. */ + unsigned brp_num = 0; + for (bp = target->breakpoints; bp; bp = bp->next) + { + struct arm11_sc7_action brp[2]; - /* Set up breakpoint for stepping */ + brp[0].write = 1; + brp[0].address = ARM11_SC7_BVR0 + brp_num; + brp[0].value = bp->address; + brp[1].write = 1; + brp[1].address = ARM11_SC7_BCR0 + brp_num; + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); - arm11_sc7_action_t brp[2]; + arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)); - brp[0].write = 1; - brp[0].address = ARM11_SC7_BVR0; - brp[0].value = R(PC); - brp[1].write = 1; - brp[1].address = ARM11_SC7_BCR0; - brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21); + LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num, + bp->address); - arm11_sc7_run(arm11, brp, asizeof(brp)); + brp_num++; + } - /* resume */ + arm11_sc7_set_vcr(arm11, arm11_vcr); + } arm11_leave_debug_state(arm11); - arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI); - - jtag_execute_queue(); + arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE); - /** \todo TODO: add a timeout */ - - /* wait for halt */ + CHECK_RETVAL(jtag_execute_queue()); + int i = 0; while (1) { - u32 dscr = arm11_read_DSCR(arm11); - - DEBUG("DSCR %08x", dscr); - - if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) == - (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) - break; + uint32_t dscr; + + CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); + + LOG_DEBUG("DSCR %08" PRIx32 "", dscr); + + if (dscr & ARM11_DSCR_CORE_RESTARTED) + break; + + + long long then = 0; + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + i++; } - /* clear breakpoint */ - arm11_sc7_clear_vbw(arm11); - - /* save state */ - arm11_on_enter_debug_state(arm11); - } + if (!debug_execution) + { + target->state = TARGET_RUNNING; + target->debug_reason = DBG_REASON_NOTHALTED; -// target->state = TARGET_HALTED; - target->debug_reason = DBG_REASON_SINGLESTEP; + CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); + } + else + { + target->state = TARGET_DEBUG_RUNNING; + target->debug_reason = DBG_REASON_NOTHALTED; - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); + } - return ERROR_OK; + return ERROR_OK; } - -/* target reset control */ -int arm11_assert_reset(struct target_s *target) +static int arm11_step(struct target *target, int current, + uint32_t address, int handle_breakpoints) { - FNC_INFO; + LOG_DEBUG("target->state: %s", + target_state_name(target)); -#if 0 - /* assert reset lines */ - /* resets only the DBGTAP, not the ARM */ + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target was not halted"); + return ERROR_TARGET_NOT_HALTED; + } - jtag_add_reset(1, 0); - jtag_add_sleep(5000); + struct arm11_common *arm11 = target_to_arm11(target); - arm11_common_t * arm11 = target->arch_info; - arm11->trst_active = true; -#endif + address = arm11_nextpc(arm11, current, address); - return ERROR_OK; -} + LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : ""); -int arm11_deassert_reset(struct target_s *target) -{ - FNC_INFO; - -#if 0 - DEBUG("target->state: %s", target_state_strings[target->state]); - /* deassert reset lines */ - jtag_add_reset(0, 0); + /** \todo TODO: Thumb not supported here */ - arm11_common_t * arm11 = target->arch_info; - arm11->trst_active = false; + uint32_t next_instruction; - if (arm11->halt_requested) - return arm11_halt(target); -#endif + CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction)); - return ERROR_OK; -} + /* skip over BKPT */ + if ((next_instruction & 0xFFF00070) == 0xe1200070) + { + address = arm11_nextpc(arm11, 0, address + 4); + LOG_DEBUG("Skipping BKPT"); + } + /* skip over Wait for interrupt / Standby */ + /* mcr 15, 0, r?, cr7, cr0, {4} */ + else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) + { + address = arm11_nextpc(arm11, 0, address + 4); + LOG_DEBUG("Skipping WFI"); + } + /* ignore B to self */ + else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe) + { + LOG_DEBUG("Not stepping jump to self"); + } + else + { + /** \todo TODO: check if break-/watchpoints make any sense at all in combination + * with this. */ + + /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively + * the VCR might be something worth looking into. */ + + + /* Set up breakpoint for stepping */ + + struct arm11_sc7_action brp[2]; + + brp[0].write = 1; + brp[0].address = ARM11_SC7_BVR0; + brp[1].write = 1; + brp[1].address = ARM11_SC7_BCR0; + + if (arm11_config_hardware_step) + { + /* Hardware single stepping ("instruction address + * mismatch") is used if enabled. It's not quite + * exactly "run one instruction"; "branch to here" + * loops won't break, neither will some other cases, + * but it's probably the best default. + * + * Hardware single stepping isn't supported on v6 + * debug modules. ARM1176 and v7 can support it... + * + * FIXME Thumb stepping likely needs to use 0x03 + * or 0xc0 byte masks, not 0x0f. + */ + brp[0].value = address; + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) + | (0 << 14) | (0 << 16) | (0 << 20) + | (2 << 21); + } else + { + /* Sets a breakpoint on the next PC, as calculated + * by instruction set simulation. + * + * REVISIT stepping Thumb on ARM1156 requires Thumb2 + * support from the simulator. + */ + uint32_t next_pc; + int retval; + + retval = arm_simulate_step(target, &next_pc); + if (retval != ERROR_OK) + return retval; + + brp[0].value = next_pc; + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) + | (0 << 14) | (0 << 16) | (0 << 20) + | (0 << 21); + } + + CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp))); + + /* resume */ + + + if (arm11_config_step_irq_enable) + R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */ + else + R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE; + + + CHECK_RETVAL(arm11_leave_debug_state(arm11)); + + arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE); + + CHECK_RETVAL(jtag_execute_queue()); + + /* wait for halt */ + int i = 0; + while (1) + { + uint32_t dscr; + + CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); + + LOG_DEBUG("DSCR %08" PRIx32 "e", dscr); + + if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) == + (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) + break; + + long long then = 0; + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + i++; + } + + /* clear breakpoint */ + arm11_sc7_clear_vbw(arm11); + + /* save state */ + CHECK_RETVAL(arm11_on_enter_debug_state(arm11)); + + /* restore default state */ + R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; -int arm11_soft_reset_halt(struct target_s *target) -{ - FNC_INFO_NOTIMPLEMENTED; + } - return ERROR_OK; -} + // target->state = TARGET_HALTED; + target->debug_reason = DBG_REASON_SINGLESTEP; -int arm11_prepare_reset_halt(struct target_s *target) -{ - FNC_INFO_NOTIMPLEMENTED; + CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED)); - return ERROR_OK; + return ERROR_OK; } - -/* target register access for gdb */ -int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size) +static int arm11_assert_reset(struct target *target) { - FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; - - *reg_list_size = ARM11_GDB_REGISTER_COUNT; - *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT); + int retval; + struct arm11_common *arm11 = target_to_arm11(target); - {size_t i; - for (i = 16; i < 24; i++) - { - (*reg_list)[i] = &arm11_gdb_dummy_fp_reg; - }} + retval = arm11_check_init(arm11, NULL); + if (retval != ERROR_OK) + return retval; - (*reg_list)[24] = &arm11_gdb_dummy_fps_reg; + target->state = TARGET_UNKNOWN; + /* we would very much like to reset into the halted, state, + * but resetting and halting is second best... */ + if (target->reset_halt) + { + CHECK_RETVAL(target_halt(target)); + } - {size_t i; - for (i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - if (arm11_reg_defs[i].gdb_num == -1) - continue; - (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i; - }} + /* srst is funny. We can not do *anything* else while it's asserted + * and it has unkonwn side effects. Make sure no other code runs + * meanwhile. + * + * Code below assumes srst: + * + * - Causes power-on-reset (but of what parts of the system?). Bug + * in arm11? + * + * - Messes us TAP state without asserting trst. + * + * - There is another bug in the arm11 core. When you generate an access to + * external logic (for example ddr controller via AHB bus) and that block + * is not configured (perhaps it is still held in reset), that transaction + * will never complete. This will hang arm11 core but it will also hang + * JTAG controller. Nothing, short of srst assertion will bring it out of + * this. + * + * Mysteries: + * + * - What should the PC be after an srst reset when starting in the halted + * state? + */ + + jtag_add_reset(0, 1); + jtag_add_reset(0, 0); + + /* How long do we have to wait? */ + jtag_add_sleep(5000); + + /* un-mess up TAP state */ + jtag_add_tlr(); + + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + { + return retval; + } - return ERROR_OK; + return ERROR_OK; } +static int arm11_deassert_reset(struct target *target) +{ + return ERROR_OK; +} -/* target memory access -* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) -* count: number of items of -*/ -int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +static int arm11_soft_reset_halt(struct target *target) { - /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */ + LOG_WARNING("Not implemented: %s", __func__); - FNC_INFO; + return ERROR_FAIL; +} - if (target->state != TARGET_HALTED) - { - WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } +/* target memory access + * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) + * count: number of items of + * + * arm11_config_memrw_no_increment - in the future we may want to be able + * to read/write a range of data to a "port". a "port" is an action on + * read memory address for some peripheral. + */ +static int arm11_read_memory_inner(struct target *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, + bool arm11_config_memrw_no_increment) +{ + /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */ + int retval; - DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count); + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target was not halted"); + return ERROR_TARGET_NOT_HALTED; + } - arm11_common_t * arm11 = target->arch_info; + LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count); - arm11_run_instr_data_prepare(arm11); + struct arm11_common *arm11 = target_to_arm11(target); - /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; - switch (size) - { - case 1: - /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */ - arm11->reg_list[ARM11_RC_R1].dirty = 1; + /* MRC p14,0,r0,c0,c5,0 */ + retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + if (retval != ERROR_OK) + return retval; - {size_t i; - for (i = 0; i < count; i++) + switch (size) { - /* ldrb r1, [r0], #1 */ - arm11_run_instr_no_data1(arm11, 0xe4d01001); - - u32 res; - /* MCR p14,0,R1,c0,c5,0 */ - arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1); + case 1: + arm11->arm.core_cache->reg_list[1].dirty = true; - *buffer++ = res; - }} + for (size_t i = 0; i < count; i++) + { + /* ldrb r1, [r0], #1 */ + /* ldrb r1, [r0] */ + arm11_run_instr_no_data1(arm11, + !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000); - break; + uint32_t res; + /* MCR p14,0,R1,c0,c5,0 */ + arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1); - case 2: - { - arm11->reg_list[ARM11_RC_R1].dirty = 1; + *buffer++ = res; + } - u16 * buf16 = (u16*)buffer; + break; - {size_t i; - for (i = 0; i < count; i++) - { - /* ldrh r1, [r0], #2 */ - arm11_run_instr_no_data1(arm11, 0xe0d010b2); + case 2: + { + arm11->arm.core_cache->reg_list[1].dirty = true; - u32 res; + for (size_t i = 0; i < count; i++) + { + /* ldrh r1, [r0], #2 */ + arm11_run_instr_no_data1(arm11, + !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0); - /* MCR p14,0,R1,c0,c5,0 */ - arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1); + uint32_t res; - *buf16++ = res; - }} + /* MCR p14,0,R1,c0,c5,0 */ + arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1); - break; - } + uint16_t svalue = res; + memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t)); + } - case 4: + break; + } - /* LDC p14,c5,[R0],#4 */ - arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count); - break; - } + case 4: + { + uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00; + /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ + uint32_t *words = (uint32_t *)buffer; - arm11_run_instr_data_finish(arm11); + /* LDC p14,c5,[R0],#4 */ + /* LDC p14,c5,[R0] */ + arm11_run_instr_data_from_core(arm11, instr, words, count); + break; + } + } - return ERROR_OK; + return arm11_run_instr_data_finish(arm11); } -int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - FNC_INFO; - - if (target->state != TARGET_HALTED) - { - WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count); - - arm11_common_t * arm11 = target->arch_info; - - arm11_run_instr_data_prepare(arm11); - - /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + return arm11_read_memory_inner(target, address, size, count, buffer, false); +} - switch (size) - { - case 1: - { - arm11->reg_list[ARM11_RC_R1].dirty = 1; +/* +* no_increment - in the future we may want to be able +* to read/write a range of data to a "port". a "port" is an action on +* read memory address for some peripheral. +*/ +static int arm11_write_memory_inner(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer, + bool no_increment) +{ + int retval; - {size_t i; - for (i = 0; i < count; i++) + if (target->state != TARGET_HALTED) { - /* MRC p14,0,r1,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); - - /* strb r1, [r0], #1 */ - arm11_run_instr_no_data1(arm11, 0xe4c01001); - }} - - break; - } - - case 2: - { - arm11->reg_list[ARM11_RC_R1].dirty = 1; + LOG_WARNING("target was not halted"); + return ERROR_TARGET_NOT_HALTED; + } - u16 * buf16 = (u16*)buffer; + LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count); - {size_t i; - for (i = 0; i < count; i++) - { - /* MRC p14,0,r1,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++); + struct arm11_common *arm11 = target_to_arm11(target); - /* strh r1, [r0], #2 */ - arm11_run_instr_no_data1(arm11, 0xe0c010b2); - }} + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; - break; - } + /* MRC p14,0,r0,c0,c5,0 */ + retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + if (retval != ERROR_OK) + return retval; - case 4: - /** \todo TODO: check if buffer cast to u32* might cause alignment problems */ + /* burst writes are not used for single words as those may well be + * reset init script writes. + * + * The other advantage is that as burst writes are default, we'll + * now exercise both burst and non-burst code paths with the + * default settings, increasing code coverage. + */ + bool burst = arm11_config_memwrite_burst && (count > 1); - if (!arm11_config_memwrite_burst) + switch (size) { - /* STC p14,c5,[R0],#4 */ - arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count); + case 1: + { + arm11->arm.core_cache->reg_list[1].dirty = true; + + for (size_t i = 0; i < count; i++) + { + /* MRC p14,0,r1,c0,c5,0 */ + retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); + if (retval != ERROR_OK) + return retval; + + /* strb r1, [r0], #1 */ + /* strb r1, [r0] */ + retval = arm11_run_instr_no_data1(arm11, + !no_increment + ? 0xe4c01001 + : 0xe5c01000); + if (retval != ERROR_OK) + return retval; + } + + break; + } + + case 2: + { + arm11->arm.core_cache->reg_list[1].dirty = true; + + for (size_t i = 0; i < count; i++) + { + uint16_t value; + memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t)); + + /* MRC p14,0,r1,c0,c5,0 */ + retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value); + if (retval != ERROR_OK) + return retval; + + /* strh r1, [r0], #2 */ + /* strh r1, [r0] */ + retval = arm11_run_instr_no_data1(arm11, + !no_increment + ? 0xe0c010b2 + : 0xe1c010b0); + if (retval != ERROR_OK) + return retval; + } + + break; + } + + case 4: { + uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00; + + /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ + uint32_t *words = (uint32_t*)buffer; + + if (!burst) + { + /* STC p14,c5,[R0],#4 */ + /* STC p14,c5,[R0]*/ + retval = arm11_run_instr_data_to_core(arm11, instr, words, count); + if (retval != ERROR_OK) + return retval; + } + else + { + /* STC p14,c5,[R0],#4 */ + /* STC p14,c5,[R0]*/ + retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count); + if (retval != ERROR_OK) + return retval; + } + + break; } - else - { - /* STC p14,c5,[R0],#4 */ - arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count); } - break; - } - -#if 1 - /* r0 verification */ - { - u32 r0; - - /* MCR p14,0,R0,c0,c5,0 */ - arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1); - - if (address + size * count != r0) + /* r0 verification */ + if (!no_increment) { - ERROR("Data transfer failed. (%d)", (r0 - address) - size * count); - - if (arm11_config_memwrite_burst) - ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode"); - - if (arm11_config_memwrite_error_fatal) - exit(-1); + uint32_t r0; + + /* MCR p14,0,R0,c0,c5,0 */ + retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1); + if (retval != ERROR_OK) + return retval; + + if (address + size * count != r0) + { + LOG_ERROR("Data transfer failed. Expected end " + "address 0x%08x, got 0x%08x", + (unsigned) (address + size * count), + (unsigned) r0); + + if (burst) + LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode"); + + if (arm11_config_memwrite_error_fatal) + return ERROR_FAIL; + } } - } -#endif - - - arm11_run_instr_data_finish(arm11); - - - - return ERROR_OK; + return arm11_run_instr_data_finish(arm11); } - -/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ -int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer) +static int arm11_write_memory(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { - FNC_INFO; - - if (target->state != TARGET_HALTED) - { - WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - return arm11_write_memory(target, address, 4, count, buffer); + /* pointer increment matters only for multi-unit writes ... + * not e.g. to a "reset the chip" controller. + */ + return arm11_write_memory_inner(target, address, size, + count, buffer, count == 1); } - -int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) +/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ +static int arm11_bulk_write_memory(struct target *target, + uint32_t address, uint32_t count, uint8_t *buffer) { - FNC_INFO_NOTIMPLEMENTED; + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target was not halted"); + return ERROR_TARGET_NOT_HALTED; + } - return ERROR_OK; + return arm11_write_memory(target, address, 4, count, buffer); } - -/* target break-/watchpoint control +/* target break-/watchpoint control * rw: 0 = write, 1 = read, 2 = access */ -int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int arm11_add_breakpoint(struct target *target, + struct breakpoint *breakpoint) { - FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); #if 0 - if (breakpoint->type == BKPT_SOFT) - { - INFO("sw breakpoint requested, but software breakpoints not enabled"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + if (breakpoint->type == BKPT_SOFT) + { + LOG_INFO("sw breakpoint requested, but software breakpoints not enabled"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } #endif - if (!arm11->free_brps) - { - INFO("no breakpoint unit available for hardware breakpoint"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + if (!arm11->free_brps) + { + LOG_DEBUG("no breakpoint unit available for hardware breakpoint"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } - if (breakpoint->length != 4) - { - INFO("only breakpoints of four bytes length supported"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + if (breakpoint->length != 4) + { + LOG_DEBUG("only breakpoints of four bytes length supported"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } - arm11->free_brps--; + arm11->free_brps--; - return ERROR_OK; + return ERROR_OK; } -int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int arm11_remove_breakpoint(struct target *target, + struct breakpoint *breakpoint) { - FNC_INFO; + struct arm11_common *arm11 = target_to_arm11(target); - arm11_common_t * arm11 = target->arch_info; - - arm11->free_brps++; + arm11->free_brps++; - return ERROR_OK; + return ERROR_OK; } -int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int arm11_add_watchpoint(struct target *target, + struct watchpoint *watchpoint) { - FNC_INFO_NOTIMPLEMENTED; + LOG_WARNING("Not implemented: %s", __func__); - return ERROR_OK; + return ERROR_FAIL; } -int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int arm11_remove_watchpoint(struct target *target, + struct watchpoint *watchpoint) { - FNC_INFO_NOTIMPLEMENTED; + LOG_WARNING("Not implemented: %s", __func__); - return ERROR_OK; + return ERROR_FAIL; } +static int arm11_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, uint32_t *value); +static int arm11_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, + uint32_t CRm, uint32_t value); -/* target algorithm support */ -int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info) -{ - FNC_INFO_NOTIMPLEMENTED; - - return ERROR_OK; -} - -int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +static int arm11_target_create(struct target *target, Jim_Interp *interp) { - FNC_INFO; + struct arm11_common *arm11; - if (argc < 4) - { - ERROR("'target arm11' 4th argument "); - exit(-1); - } + if (target->tap == NULL) + return ERROR_FAIL; - int chain_pos = strtoul(args[3], NULL, 0); - - NEW(arm11_common_t, arm11, 1); - - arm11->target = target; + if (target->tap->ir_length != 5) + { + LOG_ERROR("'target arm11' expects IR LENGTH = 5"); + return ERROR_COMMAND_SYNTAX_ERROR; + } - /* prepare JTAG information for the new target */ - arm11->jtag_info.chain_pos = chain_pos; - arm11->jtag_info.scann_size = 5; + arm11 = calloc(1, sizeof *arm11); + if (!arm11) + return ERROR_FAIL; - arm_jtag_setup_connection(&arm11->jtag_info); + armv4_5_init_arch_info(target, &arm11->arm); - jtag_device_t *device = jtag_get_device(chain_pos); + arm11->arm.mrc = arm11_mrc; + arm11->arm.mcr = arm11_mcr; - if (device->ir_length != 5) - { - ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'"); - exit(-1); - } + arm11->target = target; - target->arch_info = arm11; + arm11->jtag_info.tap = target->tap; + arm11->jtag_info.scann_size = 5; + arm11->jtag_info.scann_instr = ARM11_SCAN_N; + /* cur_scan_chain == 0 */ + arm11->jtag_info.intest_instr = ARM11_INTEST; - return ERROR_OK; + return ERROR_OK; } -int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int arm11_init_target(struct command_context *cmd_ctx, + struct target *target) { - FNC_INFO; + /* Initialize anything we can set up without talking to the target */ - arm11_common_t * arm11 = target->arch_info; + /* REVISIT do we really want such a debug-registers-only cache? + * If we do, it should probably be handled purely by the DPM code, + * so it works identically on the v7a/v7r cores. + */ + return arm11_build_reg_cache(target); +} - /* check IDCODE */ +/* talk to the target and set things up */ +static int arm11_examine(struct target *target) +{ + int retval; + char *type; + struct arm11_common *arm11 = target_to_arm11(target); + uint32_t didr, device_id; + uint8_t implementor; - arm11_add_IR(arm11, ARM11_IDCODE, -1); + /* FIXME split into do-first-time and do-every-time logic ... */ - scan_field_t idcode_field; + /* check IDCODE */ - arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field); + arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT); - arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD); + struct scan_field idcode_field; - /* check DIDR */ + arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field); - arm11_add_debug_SCAN_N(arm11, 0x00, -1); + arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE); - arm11_add_IR(arm11, ARM11_INTEST, -1); + /* check DIDR */ - scan_field_t chain0_fields[2]; + arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); - arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0); - arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1); + arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI); + struct scan_field chain0_fields[2]; - jtag_execute_queue(); + arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0); + arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE); - switch (arm11->device_id & 0x0FFFF000) - { - case 0x07B36000: INFO("found ARM1136"); break; - case 0x07B56000: INFO("found ARM1156"); break; - case 0x07B76000: INFO("found ARM1176"); break; - default: - { - ERROR("'target arm11' expects IDCODE 0x*7B*7****"); - exit(-1); - } - } + CHECK_RETVAL(jtag_execute_queue()); - arm11->debug_version = (arm11->didr >> 16) & 0x0F; + switch (device_id & 0x0FFFF000) + { + case 0x07B36000: + type = "ARM1136"; + break; + case 0x07B56000: + type = "ARM1156"; + break; + case 0x07B76000: + arm11->arm.core_type = ARM_MODE_MON; + type = "ARM1176"; + break; + default: + LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****"); + return ERROR_FAIL; + } + LOG_INFO("found %s", type); - if (arm11->debug_version != ARM11_DEBUG_V6 && - arm11->debug_version != ARM11_DEBUG_V61) - { - ERROR("Only ARMv6 v6 and v6.1 architectures supported."); - exit(-1); - } + /* unlikely this could ever fail, but ... */ + switch ((didr >> 16) & 0x0F) { + case ARM11_DEBUG_V6: + case ARM11_DEBUG_V61: /* supports security extensions */ + break; + default: + LOG_ERROR("Only ARM v6 and v6.1 debug supported."); + return ERROR_FAIL; + } + arm11->brp = ((didr >> 24) & 0x0F) + 1; + arm11->wrp = ((didr >> 28) & 0x0F) + 1; - arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1; - arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1; + /** \todo TODO: reserve one brp slot if we allow breakpoints during step */ + arm11->free_brps = arm11->brp; + arm11->free_wrps = arm11->wrp; - /** \todo TODO: reserve one brp slot if we allow breakpoints during step */ - arm11->free_brps = arm11->brp; - arm11->free_wrps = arm11->wrp; + LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32, + device_id, implementor, didr); - DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x", - arm11->device_id, - arm11->implementor, - arm11->didr); + /* as a side-effect this reads DSCR and thus + * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag + * as suggested by the spec. + */ - arm11_build_reg_cache(target); + retval = arm11_check_init(arm11, NULL); + if (retval != ERROR_OK) + return retval; + /* Build register cache "late", after target_init(), since we + * want to know if this core supports Secure Monitor mode. + */ + if (!target_was_examined(target)) { + arm11_dpm_init(arm11, didr); + retval = arm_dpm_setup(&arm11->dpm); + } - /* as a side-effect this reads DSCR and thus - * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag - * as suggested by the spec. - */ + /* ETM on ARM11 still uses original scanchain 6 access mode */ + if (arm11->arm.etm && !target_was_examined(target)) { + *register_get_last_cache_p(&target->reg_cache) = + etm_build_reg_cache(target, &arm11->jtag_info, + arm11->arm.etm); + retval = etm_setup(target); + } - arm11_check_init(arm11, NULL); + target_set_examined(target); - return ERROR_OK; + return ERROR_OK; } -int arm11_quit(void) -{ - FNC_INFO_NOTIMPLEMENTED; - - return ERROR_OK; -} /** Load a register that is marked !valid in the register cache */ -int arm11_get_reg(reg_t *reg) +static int arm11_get_reg(struct reg *reg) { - FNC_INFO; - - target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target; + struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target; - if (target->state != TARGET_HALTED) - { - WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target was not halted"); + return ERROR_TARGET_NOT_HALTED; + } - /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */ + /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */ #if 0 - arm11_common_t *arm11 = target->arch_info; - const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; + struct arm11_common *arm11 = target_to_arm11(target); + const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index; #endif - return ERROR_OK; + return ERROR_OK; } /** Change a value in the register cache */ -int arm11_set_reg(reg_t *reg, u8 *buf) +static int arm11_set_reg(struct reg *reg, uint8_t *buf) { - FNC_INFO; - - target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target; - arm11_common_t *arm11 = target->arch_info; -// const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; - - arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32); - reg->valid = 1; - reg->dirty = 1; - - return ERROR_OK; -} + struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target; + struct arm11_common *arm11 = target_to_arm11(target); +// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index; + arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32); + reg->valid = 1; + reg->dirty = 1; -void arm11_build_reg_cache(target_t *target) -{ - arm11_common_t *arm11 = target->arch_info; - - NEW(reg_cache_t, cache, 1); - NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT); - NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT); - - if (arm11_regs_arch_type == -1) - arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg); - - arm11->reg_list = reg_list; - - /* Build the process context cache */ - cache->name = "arm11 registers"; - cache->next = NULL; - cache->reg_list = reg_list; - cache->num_regs = ARM11_REGCACHE_COUNT; - - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - (*cache_p) = cache; - -// armv7m->core_cache = cache; -// armv7m->process_context = cache; - - size_t i; - - /* Not very elegant assertion */ - if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) || - ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) || - ARM11_REGCACHE_COUNT != ARM11_RC_MAX) - { - ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX); - exit(-1); - } - - for (i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - reg_t * r = reg_list + i; - const arm11_reg_defs_t * rd = arm11_reg_defs + i; - arm11_reg_state_t * rs = arm11_reg_states + i; - - r->name = rd->name; - r->size = 32; - r->value = (u8 *)(arm11->reg_values + i); - r->dirty = 0; - r->valid = 0; - r->bitfield_desc = NULL; - r->num_bitfields = 0; - r->arch_type = arm11_regs_arch_type; - r->arch_info = rs; - - rs->def_index = i; - rs->target = target; - } + return ERROR_OK; } +static const struct reg_arch_type arm11_reg_type = { + .get = arm11_get_reg, + .set = arm11_set_reg, +}; - -int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name) +static int arm11_build_reg_cache(struct target *target) { - if (argc == 0) - { - INFO("%s is %s.", name, *var ? "enabled" : "disabled"); - return ERROR_OK; - } - - if (argc != 1) - return ERROR_COMMAND_SYNTAX_ERROR; - - switch (args[0][0]) - { - case '0': /* 0 */ - case 'f': /* false */ - case 'F': - case 'd': /* disable */ - case 'D': - *var = false; - break; - - case '1': /* 1 */ - case 't': /* true */ - case 'T': - case 'e': /* enable */ - case 'E': - *var = true; - break; - } - - INFO("%s %s.", *var ? "Enabled" : "Disabled", name); - - return ERROR_OK; -} - + struct arm11_common *arm11 = target_to_arm11(target); + struct reg_cache *cache; + struct reg *reg_list; + struct arm11_reg_state *arm11_reg_states; + + cache = calloc(1, sizeof *cache); + reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list); + arm11_reg_states = calloc(ARM11_REGCACHE_COUNT, + sizeof *arm11_reg_states); + if (!cache || !reg_list || !arm11_reg_states) { + free(cache); + free(reg_list); + free(arm11_reg_states); + return ERROR_FAIL; + } -#define BOOL_WRAPPER(name, print_name) \ -int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \ -{ \ - return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \ -} + arm11->reg_list = reg_list; -#define RC_TOP(name, descr, more) \ -{ \ - command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \ - command_t * top_cmd = new_cmd; \ - more \ -} + /* build cache for some of the debug registers */ + cache->name = "arm11 debug registers"; + cache->reg_list = reg_list; + cache->num_regs = ARM11_REGCACHE_COUNT; -#define RC_FINAL(name, descr, handler) \ - register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr); + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + (*cache_p) = cache; -#define RC_FINAL_BOOL(name, descr, var) \ - register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr); + arm11->core_cache = cache; + size_t i; -BOOL_WRAPPER(memwrite_burst, "memory write burst mode") -BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes") + /* Not very elegant assertion */ + if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) || + ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) || + ARM11_REGCACHE_COUNT != ARM11_RC_MAX) + { + LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)", + ARM11_REGCACHE_COUNT, + (unsigned) ARRAY_SIZE(arm11->reg_values), + (unsigned) ARRAY_SIZE(arm11_reg_defs), + ARM11_RC_MAX); + /* FIXME minimally, use a build_bug_on(X) mechanism; + * runtime exit() here is bad! + */ + exit(-1); + } + for (i = 0; i < ARM11_REGCACHE_COUNT; i++) + { + struct reg * r = reg_list + i; + const struct arm11_reg_defs * rd = arm11_reg_defs + i; + struct arm11_reg_state * rs = arm11_reg_states + i; + + r->name = rd->name; + r->size = 32; + r->value = (uint8_t *)(arm11->reg_values + i); + r->dirty = 0; + r->valid = 0; + r->type = &arm11_reg_type; + r->arch_info = rs; + + rs->def_index = i; + rs->target = target; + } -int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - if (argc == 1) - { - arm11_vcr = strtoul(args[0], NULL, 0); - } - else if (argc != 0) - { - return ERROR_COMMAND_SYNTAX_ERROR; - } - - INFO("VCR 0x%08X", arm11_vcr); - return ERROR_OK; + return ERROR_OK; } -const u32 arm11_coproc_instruction_limits[] = -{ - 15, /* coprocessor */ - 7, /* opcode 1 */ - 15, /* CRn */ - 15, /* CRm */ - 7, /* opcode 2 */ - 0xFFFFFFFF, /* value */ -}; +/* FIXME all these BOOL_WRAPPER things should be modifying + * per-instance state, not shared state; ditto the vector + * catch register support. Scan chains with multiple cores + * should be able to say "work with this core like this, + * that core like that". Example, ARM11 MPCore ... + */ -const char arm11_mrc_syntax[] = "Syntax: mrc . All parameters are numbers only."; -const char arm11_mcr_syntax[] = "Syntax: mcr <32bit value to write>. All parameters are numbers only."; +#define ARM11_BOOL_WRAPPER(name, print_name) \ + COMMAND_HANDLER(arm11_handle_bool_##name) \ + { \ + return CALL_COMMAND_HANDLER(handle_command_parse_bool, \ + &arm11_config_##name, print_name); \ + } +ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode") +ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes") +ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping") +ARM11_BOOL_WRAPPER(hardware_step, "hardware single step") -arm11_common_t * arm11_find_target(const char * arg) +COMMAND_HANDLER(arm11_handle_vcr) { - size_t jtag_target = strtoul(arg, NULL, 0); - - {target_t * t; - for (t = targets; t; t = t->next) - { - if (t->type != &arm11_target) - continue; - - arm11_common_t * arm11 = t->arch_info; - - if (arm11->jtag_info.chain_pos != jtag_target) - continue; - - return arm11; - }} + switch (CMD_ARGC) { + case 0: + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } - return 0; + LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr); + return ERROR_OK; } -int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read) +static const uint32_t arm11_coproc_instruction_limits[] = { - if (argc != (read ? 6 : 7)) - { - ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax); - return -1; - } - - arm11_common_t * arm11 = arm11_find_target(args[0]); - - if (!arm11) - { - ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s", - read ? arm11_mrc_syntax : arm11_mcr_syntax); - - return -1; - - } - - if (arm11->target->state != TARGET_HALTED) - { - WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - - u32 values[6]; + 15, /* coprocessor */ + 7, /* opcode 1 */ + 15, /* CRn */ + 15, /* CRm */ + 7, /* opcode 2 */ + 0xFFFFFFFF, /* value */ +}; - {size_t i; - for (i = 0; i < (read ? 5 : 6); i++) - { - values[i] = strtoul(args[i + 1], NULL, 0); +static int arm11_mrc_inner(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, + uint32_t *value, bool read) +{ + int retval; + struct arm11_common *arm11 = target_to_arm11(target); - if (values[i] > arm11_coproc_instruction_limits[i]) + if (target->state != TARGET_HALTED) { - ERROR("Parameter %d out of bounds (%d max). %s", - i + 2, arm11_coproc_instruction_limits[i], - read ? arm11_mrc_syntax : arm11_mcr_syntax); - return -1; + LOG_ERROR("Target not halted"); + return ERROR_FAIL; } - }} - - u32 instr = 0xEE000010 | - (values[0] << 8) | - (values[1] << 21) | - (values[2] << 16) | - (values[3] << 0) | - (values[4] << 5); - - if (read) - instr |= 0x00100000; - - - arm11_run_instr_data_prepare(arm11); - - if (read) - { - u32 result; - arm11_run_instr_data_from_core_via_r0(arm11, instr, &result); - INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)", - values[0], values[1], values[2], values[3], values[4], result, result); - } - else - { - arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]); + uint32_t instr = 0xEE000010 | + (cpnum << 8) | + (op1 << 21) | + (CRn << 16) | + (CRm << 0) | + (op2 << 5); - INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d", - values[0], values[1], - values[5], - values[2], values[3], values[4]); - } + if (read) + instr |= 0x00100000; - arm11_run_instr_data_finish(arm11); + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; + if (read) + { + retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value); + if (retval != ERROR_OK) + return retval; + } + else + { + retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value); + if (retval != ERROR_OK) + return retval; + } - return ERROR_OK; + return arm11_run_instr_data_finish(arm11); } -int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int arm11_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { - return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true); + return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true); } -int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int arm11_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { - return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false); + return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false); } -int arm11_register_commands(struct command_context_s *cmd_ctx) -{ - FNC_INFO; +static const struct command_registration arm11_mw_command_handlers[] = { + { + .name = "burst", + .handler = &arm11_handle_bool_memwrite_burst, + .mode = COMMAND_ANY, + .help = "Enable/Disable non-standard but fast burst mode" + " (default: enabled)", + }, + { + .name = "error_fatal", + .handler = &arm11_handle_bool_memwrite_error_fatal, + .mode = COMMAND_ANY, + .help = "Terminate program if transfer error was found" + " (default: enabled)", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration arm11_any_command_handlers[] = { + { + /* "hardware_step" is only here to check if the default + * simulate + breakpoint implementation is broken. + * TEMPORARY! NOT DOCUMENTED! */ + .name = "hardware_step", + .handler = &arm11_handle_bool_hardware_step, + .mode = COMMAND_ANY, + .help = "DEBUG ONLY - Hardware single stepping" + " (default: disabled)", + .usage = "(enable|disable)", + }, + { + .name = "memwrite", + .mode = COMMAND_ANY, + .help = "memwrite command group", + .chain = arm11_mw_command_handlers, + }, + { + .name = "step_irq_enable", + .handler = &arm11_handle_bool_step_irq_enable, + .mode = COMMAND_ANY, + .help = "Enable interrupts while stepping" + " (default: disabled)", + }, + { + .name = "vcr", + .handler = &arm11_handle_vcr, + .mode = COMMAND_ANY, + .help = "Control (Interrupt) Vector Catch Register", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration arm11_command_handlers[] = { + { + .chain = arm_command_handlers, + }, + { + .chain = etm_command_handlers, + }, + { + .name = "arm11", + .mode = COMMAND_ANY, + .help = "ARM11 command group", + .chain = arm11_any_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; - command_t * top_cmd = NULL; +/** Holds methods for ARM11xx targets. */ +struct target_type arm11_target = { + .name = "arm11", - RC_TOP( "arm11", "arm11 specific commands", + .poll = arm11_poll, + .arch_state = arm11_arch_state, - RC_TOP( "memwrite", "Control memory write transfer mode", + .target_request_data = arm11_target_request_data, - RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)", - memwrite_burst) + .halt = arm11_halt, + .resume = arm11_resume, + .step = arm11_step, - RC_FINAL_BOOL( "error_fatal", - "Terminate program if transfer error was found (default: enabled)", - memwrite_error_fatal) - ) + .assert_reset = arm11_assert_reset, + .deassert_reset = arm11_deassert_reset, + .soft_reset_halt = arm11_soft_reset_halt, - RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register", - arm11_handle_vcr) + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - RC_FINAL( "mrc", "Read Coprocessor register", - arm11_handle_mrc) + .read_memory = arm11_read_memory, + .write_memory = arm11_write_memory, - RC_FINAL( "mcr", "Write Coprocessor register", - arm11_handle_mcr) - ) + .bulk_write_memory = arm11_bulk_write_memory, - return ERROR_OK; -} + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .add_breakpoint = arm11_add_breakpoint, + .remove_breakpoint = arm11_remove_breakpoint, + .add_watchpoint = arm11_add_watchpoint, + .remove_watchpoint = arm11_remove_watchpoint, + + .run_algorithm = armv4_5_run_algorithm, + + .commands = arm11_command_handlers, + .target_create = arm11_target_create, + .init_target = arm11_init_target, + .examine = arm11_examine, +};