X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=6e007cfa41ce0dbbc0abeddf1074b52cac2c05f7;hb=94dba423137d25fbe898fe7b04c451c6225a0079;hp=cdeb420039718dc947ea0ce73e8f7945c37ebc00;hpb=db094c2e60176b3c63ce788159b04a7024ad1010;p=openocd.git diff --git a/src/target/arm11.c b/src/target/arm11.c index cdeb420039..6e007cfa41 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -26,14 +26,14 @@ #include "config.h" #endif -#include "arm11.h" +#include "etm.h" #include "breakpoints.h" #include "arm11_dbgtap.h" -#include "armv4_5.h" #include "arm_simulator.h" #include "time_support.h" #include "target_type.h" #include "algorithm.h" +#include "register.h" #if 0 @@ -58,8 +58,6 @@ static uint32_t arm11_vcr = 0; static bool arm11_config_step_irq_enable = false; static bool arm11_config_hardware_step = false; -static int arm11_regs_arch_type = -1; - enum arm11_regtype { ARM11_REGISTER_CORE, @@ -248,38 +246,6 @@ enum arm11_regcache_ids #define ARM11_GDB_REGISTER_COUNT 26 -/* FIXME these are *identical* to the ARMv4_5 dummies ... except - * for their names, and being static vs global, and having different - * addresses. Ditto ARMv7a and ARMv7m dummies. - */ - -static uint8_t arm11_gdb_dummy_fp_value[12]; - -static struct reg arm11_gdb_dummy_fp_reg = -{ - .name = "GDB dummy floating-point register", - .value = arm11_gdb_dummy_fp_value, - .dirty = 0, - .valid = 1, - .size = 96, - .arch_info = NULL, - .arch_type = 0, -}; - -static uint8_t arm11_gdb_dummy_fps_value[4]; - -static struct reg arm11_gdb_dummy_fps_reg = -{ - .name = "GDB dummy floating-point status register", - .value = arm11_gdb_dummy_fps_value, - .dirty = 0, - .valid = 1, - .size = 32, - .arch_info = NULL, - .arch_type = 0, -}; - - static int arm11_on_enter_debug_state(struct arm11_common *arm11); static int arm11_step(struct target *target, int current, uint32_t address, int handle_breakpoints); @@ -362,7 +328,7 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) int retval; FNC_INFO; - for (size_t i = 0; i < asizeof(arm11->reg_values); i++) + for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++) { arm11->reg_list[i].valid = 1; arm11->reg_list[i].dirty = 0; @@ -385,7 +351,7 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); } else { @@ -665,7 +631,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11) arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); } arm11_record_register_history(arm11); @@ -876,7 +842,7 @@ static int arm11_resume(struct target *target, int current, brp[1].address = ARM11_SC7_BCR0 + brp_num; brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); - arm11_sc7_run(arm11, brp, asizeof(brp)); + arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)); LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address); @@ -1119,7 +1085,7 @@ static int arm11_step(struct target *target, int current, brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); } - CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp))); + CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp))); /* resume */ @@ -1269,12 +1235,10 @@ static int arm11_get_gdb_reg_list(struct target *target, *reg_list_size = ARM11_GDB_REGISTER_COUNT; *reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT); + /* nine unused legacy FPA registers are expected by GDB */ for (size_t i = 16; i < 24; i++) - { - (*reg_list)[i] = &arm11_gdb_dummy_fp_reg; - } - - (*reg_list)[24] = &arm11_gdb_dummy_fps_reg; + (*reg_list)[i] = &arm_gdb_dummy_fp_reg; + (*reg_list)[24] = &arm_gdb_dummy_fps_reg; for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++) { @@ -1639,7 +1603,7 @@ static int arm11_run_algorithm(struct target *target, } // FIXME -// if (armv4_5_mode_to_number(arm11->core_mode)==-1) +// if (!is_arm_mode(arm11->core_mode)) // return ERROR_FAIL; // Save regs @@ -1664,13 +1628,13 @@ static int arm11_run_algorithm(struct target *target, if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } if (reg->size != reg_params[i].size) { LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } arm11_set_reg(reg,reg_params[i].value); // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val); @@ -1749,13 +1713,15 @@ static int arm11_run_algorithm(struct target *target, if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - exit(-1); + retval = ERROR_INVALID_ARGUMENTS; + goto del_breakpoint; } if (reg->size != reg_params[i].size) { LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - exit(-1); + retval = ERROR_INVALID_ARGUMENTS; + goto del_breakpoint; } buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32)); @@ -1814,6 +1780,11 @@ static int arm11_init_target(struct command_context *cmd_ctx, struct target *target) { /* Initialize anything we can set up without talking to the target */ + + /* FIXME Switch to use the standard build_reg_cache() not custom + * code. Do it from examine(), after we check whether we're + * an arm1176 and thus support the Secure Monitor mode. + */ return arm11_build_reg_cache(target); } @@ -1821,7 +1792,7 @@ static int arm11_init_target(struct command_context *cmd_ctx, static int arm11_examine(struct target *target) { int retval; - + char *type; FNC_INFO; struct arm11_common *arm11 = target_to_arm11(target); @@ -1846,19 +1817,27 @@ static int arm11_examine(struct target *target) arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0); arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1); - arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); switch (arm11->device_id & 0x0FFFF000) { - case 0x07B36000: LOG_INFO("found ARM1136"); break; - case 0x07B56000: LOG_INFO("found ARM1156"); break; - case 0x07B76000: LOG_INFO("found ARM1176"); break; + case 0x07B36000: + type = "ARM1136"; + break; + case 0x07B56000: + type = "ARM1156"; + break; + case 0x07B76000: + arm11->arm.core_type = ARM_MODE_MON; + type = "ARM1176"; + break; default: LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****"); return ERROR_FAIL; } + LOG_INFO("found %s", type); arm11->debug_version = (arm11->didr >> 16) & 0x0F; @@ -1943,6 +1922,11 @@ static int arm11_set_reg(struct reg *reg, uint8_t *buf) return ERROR_OK; } +static const struct reg_arch_type arm11_reg_type = { + .get = arm11_get_reg, + .set = arm11_set_reg, +}; + static int arm11_build_reg_cache(struct target *target) { struct arm11_common *arm11 = target_to_arm11(target); @@ -1951,12 +1935,6 @@ static int arm11_build_reg_cache(struct target *target) NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT); NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT); - if (arm11_regs_arch_type == -1) - arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg); - - register_init_dummy(&arm11_gdb_dummy_fp_reg); - register_init_dummy(&arm11_gdb_dummy_fps_reg); - arm11->reg_list = reg_list; /* Build the process context cache */ @@ -1974,11 +1952,11 @@ static int arm11_build_reg_cache(struct target *target) size_t i; /* Not very elegant assertion */ - if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) || - ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) || + if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) || + ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) || ARM11_REGCACHE_COUNT != ARM11_RC_MAX) { - LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX); + LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, ARRAY_SIZE(arm11->reg_values), ARRAY_SIZE(arm11_reg_defs), ARM11_RC_MAX); exit(-1); } @@ -1993,7 +1971,7 @@ static int arm11_build_reg_cache(struct target *target) r->value = (uint8_t *)(arm11->reg_values + i); r->dirty = 0; r->valid = 0; - r->arch_type = arm11_regs_arch_type; + r->type = &arm11_reg_type; r->arch_info = rs; rs->def_index = i; @@ -2005,16 +1983,16 @@ static int arm11_build_reg_cache(struct target *target) static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name) { - if (argc == 0) + if (CMD_ARGC == 0) { LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled"); return ERROR_OK; } - if (argc != 1) + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - switch (args[0][0]) + switch (CMD_ARGV[0][0]) { case '0': /* 0 */ case 'f': /* false */ @@ -2052,11 +2030,11 @@ BOOL_WRAPPER(hardware_step, "hardware single step") COMMAND_HANDLER(arm11_handle_vcr) { - switch (argc) { + switch (CMD_ARGC) { case 0: break; case 1: - COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr); break; default: return ERROR_COMMAND_SYNTAX_ERROR; @@ -2137,6 +2115,8 @@ static int arm11_register_commands(struct command_context *cmd_ctx) struct command *top_cmd, *mw_cmd; + armv4_5_register_commands(cmd_ctx); + top_cmd = register_command(cmd_ctx, NULL, "arm11", NULL, COMMAND_ANY, NULL);