X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2FMakefile.am;h=05f174870015938ee355d0c94ccf83c1f2d20c87;hb=29c81a80510aa82b1842b15a9b091a3062cb51dc;hp=fcc23adbe506946a930dd8349cd72b6dba624e91;hpb=2517bae6c1438350255dca63e7d1c1e06c64b6bb;p=openocd.git

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index fcc23adbe5..05f1748700 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -4,7 +4,9 @@ else
 OOCD_TRACE_FILES =
 endif
 
-%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
+%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
+	%D%/riscv/libriscv.la
+
 
 STARTUP_TCL_SRCS += %D%/startup.tcl
 
@@ -21,6 +23,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
 	$(NDS32_SRC) \
 	$(STM8_SRC) \
 	$(INTEL_IA32_SRC) \
+	$(ESIRISC_SRC) \
 	%D%/avrt.c \
 	%D%/dsp563xx.c \
 	%D%/dsp563xx_once.c \
@@ -73,7 +76,8 @@ ARMV7_SRC = \
 	%D%/cortex_m.c \
 	%D%/armv7a.c \
 	%D%/cortex_a.c \
-	%D%/ls1_sap.c
+	%D%/ls1_sap.c \
+	%D%/mem_ap.c
 
 ARMV8_SRC = \
 	%D%/armv8_dpm.c \
@@ -136,6 +140,10 @@ INTEL_IA32_SRC = \
 	%D%/lakemont.c \
 	%D%/x86_32_common.c
 
+ESIRISC_SRC = \
+	%D%/esirisc.c \
+	%D%/esirisc_jtag.c
+
 %C%_libtarget_la_SOURCES += \
 	%D%/algorithm.h \
 	%D%/arm.h \
@@ -215,6 +223,10 @@ INTEL_IA32_SRC = \
 	%D%/stm8.h \
 	%D%/lakemont.h \
 	%D%/x86_32_common.h \
-	%D%/arm_cti.h
+	%D%/arm_cti.h \
+	%D%/esirisc.h \
+	%D%/esirisc_jtag.h \
+	%D%/esirisc_regs.h
 
 include %D%/openrisc/Makefile.am
+include %D%/riscv/Makefile.am