X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Fjtag%2Fbitbang.c;h=0f462a83ad956dfcfeff1bcf241615cf4bd1c9e8;hb=a28eaa85f73759bb189a46308642502c9fa5aa4b;hp=79f77b5624bb4ea3b636acb3dbe6c9c001679bb3;hpb=2585fc34200938fb3fa55a450ea37f68012aafa7;p=openocd.git

diff --git a/src/jtag/bitbang.c b/src/jtag/bitbang.c
index 79f77b5624..0f462a83ad 100644
--- a/src/jtag/bitbang.c
+++ b/src/jtag/bitbang.c
@@ -2,6 +2,9 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
+ *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   oyvind.harboe@zylin.com                                               *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -36,6 +39,27 @@
 
 bitbang_interface_t *bitbang_interface;
 
+
+/* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
+ * 
+ * Set this to 1 and str912 reset halt will fail.
+ * 
+ * If someone can submit a patch with an explanation it will be greatly
+ * appreciated, but as far as I can tell (ØH) DCLK is generated upon
+ * clk=0 in TAP_RTI. Good luck deducing that from the ARM documentation!
+ * The ARM documentation uses the term "DCLK is asserted while in the TAP_RTI 
+ * state". With hardware there is no such thing as *while* in a state. There
+ * are only edges. So clk => 0 is in fact a very subtle state transition that
+ * happens *while* in the TAP_RTI state. "#&¤"#¤&"#&"#&
+ * 
+ * For "reset halt" the last thing that happens before srst is asserted
+ * is that the breakpoint is set up. If DCLK is not wiggled one last
+ * time before the reset, then the breakpoint is not set up and
+ * "reset halt" will fail to halt.
+ * 
+ */
+#define CLOCK_IDLE() 0 
+
 int bitbang_execute_queue(void);
 
 /* The bitbang driver leaves the TCK 0 when in idle */
@@ -62,7 +86,7 @@ void bitbang_state_move(void) {
 		bitbang_interface->write(0, tms, 0);
 		bitbang_interface->write(1, tms, 0);
 	}
-	bitbang_interface->write(0, tms, 0);
+	bitbang_interface->write(CLOCK_IDLE(), tms, 0);
 	
 	cur_state = end_state;
 }
@@ -98,7 +122,7 @@ void bitbang_path_move(pathmove_command_t *cmd)
 		num_states--;
 	}
 	
-	bitbang_interface->write(0, tms, 0);
+	bitbang_interface->write(CLOCK_IDLE(), tms, 0);
 
 	end_state = cur_state;
 }
@@ -117,12 +141,12 @@ void bitbang_runtest(int num_cycles)
 	}
 	
 	/* execute num_cycles */
-	bitbang_interface->write(0, 0, 0);
 	for (i = 0; i < num_cycles; i++)
 	{
-		bitbang_interface->write(1, 0, 0);
 		bitbang_interface->write(0, 0, 0);
+		bitbang_interface->write(1, 0, 0);
 	}
+	bitbang_interface->write(CLOCK_IDLE(), 0, 0);
 	
 	/* finish in end_state */
 	bitbang_end_state(saved_end_state);
@@ -148,35 +172,33 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
 
 	for (bit_cnt = 0; bit_cnt < scan_size; bit_cnt++)
 	{
+		int val=0;
+		int tms=(bit_cnt==scan_size-1) ? 1 : 0;
+		int tdi;
+		int bytec=bit_cnt/8;
+		int bcval=1<<(bit_cnt % 8);
+
 		/* if we're just reading the scan, but don't care about the output
 		 * default to outputting 'low', this also makes valgrind traces more readable,
 		 * as it removes the dependency on an uninitialised value
 		 */ 
-		if ((type != SCAN_IN) && ((buffer[bit_cnt/8] >> (bit_cnt % 8)) & 0x1))
-		{
-			bitbang_interface->write(0, (bit_cnt==scan_size-1) ? 1 : 0, 1);
-			bitbang_interface->write(1, (bit_cnt==scan_size-1) ? 1 : 0, 1);
-		} else {
-			bitbang_interface->write(0, (bit_cnt==scan_size-1) ? 1 : 0, 0);
-			bitbang_interface->write(1, (bit_cnt==scan_size-1) ? 1 : 0, 0);
-		}
+		tdi=0;
+		if ((type != SCAN_IN) && (buffer[bytec] & bcval))
+			tdi=1;
+
+		bitbang_interface->write(0, tms, tdi);
+
+		if (type!=SCAN_OUT)
+			val=bitbang_interface->read();
+
+		bitbang_interface->write(1, tms, tdi);
 		
 		if (type != SCAN_OUT)
 		{
-			/*
-			TDO should be sampled on the rising edge, and will change 
-			on the falling edge. 
-			
-			Because there is no way to read the signal exactly at the rising edge,
-			read after the rising edge.
-
-			This is plain IEEE 1149 JTAG - nothing specific to the OpenOCD or its JTAG
-			API. 
-			*/
-			if (bitbang_interface->read())
-				buffer[(bit_cnt)/8] |= 1 << ((bit_cnt) % 8);
+			if (val)
+				buffer[bytec] |= bcval;
 			else
-				buffer[(bit_cnt)/8] &= ~(1 << ((bit_cnt) % 8));
+				buffer[bytec] &= ~bcval;
 		}
 	}
 	
@@ -187,7 +209,7 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
 	 */
 	bitbang_interface->write(0, 0, 0);
 	bitbang_interface->write(1, 0, 0);
-	bitbang_interface->write(0, 0, 0);
+	bitbang_interface->write(CLOCK_IDLE(), 0, 0);
 	
 	if (ir_scan)
 		cur_state = TAP_PI;