X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstr9xpec.c;h=c06e6d163dd707c1c9db3e259a1f54712fe0f248;hb=af51c69fbcc15a0dee678553adf5a864f54f58cc;hp=073dfe10fa31750abf3d7e1ef1e3157a7672791b;hpb=bc8be110ff314cab0e09792a05b6871672c18302;p=openocd.git

diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c
index 073dfe10fa..c06e6d163d 100644
--- a/src/flash/nor/str9xpec.c
+++ b/src/flash/nor/str9xpec.c
@@ -25,10 +25,59 @@
 #endif
 
 #include "imp.h"
-#include "str9xpec.h"
 #include <target/arm7_9_common.h>
 
 
+/* ISC commands */
+
+#define ISC_IDCODE				0xFE
+#define ISC_MFG_READ			0x4C
+#define ISC_CONFIGURATION		0x07
+#define ISC_ENABLE				0x0C
+#define ISC_DISABLE				0x0F
+#define ISC_NOOP				0x10
+#define ISC_ADDRESS_SHIFT		0x11
+#define ISC_CLR_STATUS			0x13
+#define ISC_PROGRAM				0x20
+#define ISC_PROGRAM_SECURITY	0x22
+#define ISC_PROGRAM_UC			0x23
+#define ISC_ERASE				0x30
+#define ISC_READ				0x50
+#define ISC_BLANK_CHECK			0x60
+
+/* ISC_DEFAULT bit definitions */
+
+#define ISC_STATUS_SECURITY		0x40
+#define ISC_STATUS_INT_ERROR	0x30
+#define ISC_STATUS_MODE			0x08
+#define ISC_STATUS_BUSY			0x04
+#define ISC_STATUS_ERROR		0x03
+
+/* Option bytes definitions */
+
+#define STR9XPEC_OPT_CSMAPBIT		48
+#define STR9XPEC_OPT_LVDTHRESBIT	49
+#define STR9XPEC_OPT_LVDSELBIT		50
+#define STR9XPEC_OPT_LVDWARNBIT		51
+#define STR9XPEC_OPT_OTPBIT			63
+
+enum str9xpec_status_codes
+{
+	STR9XPEC_INVALID_COMMAND = 1,
+	STR9XPEC_ISC_SUCCESS = 2,
+	STR9XPEC_ISC_DISABLED = 3,
+	STR9XPEC_ISC_INTFAIL = 32,
+};
+
+struct str9xpec_flash_controller
+{
+	struct jtag_tap *tap;
+	uint32_t *sector_bits;
+	int chain_pos;
+	int isc_enable;
+	uint8_t options[8];
+};
+
 static int str9xpec_erase_area(struct flash_bank *bank, int first, int last);
 static int str9xpec_set_address(struct flash_bank *bank, uint8_t sector);
 static int str9xpec_write_options(struct flash_bank *bank);
@@ -257,7 +306,8 @@ FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command)
 	arm7_9 = armv4_5->arch_info;
 	jtag_info = &arm7_9->jtag_info;
 
-	str9xpec_info->tap = bank->target->tap;
+	/* The core is the next tap after the flash controller in the chain */
+	str9xpec_info->tap = jtag_tap_by_position(jtag_info->tap->abs_chain_position - 1);
 	str9xpec_info->isc_enable = 0;
 
 	str9xpec_build_block_list(bank);
@@ -665,7 +715,7 @@ static int str9xpec_write(struct flash_bank *bank, uint8_t *buffer,
 	if (bytes_remaining)
 	{
 		uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-		int i = 0;
+		i = 0;
 
 		while (bytes_remaining > 0)
 		{
@@ -762,7 +812,7 @@ static int str9xpec_erase_check(struct flash_bank *bank)
 	return str9xpec_blank_check(bank, 0, bank->num_sectors - 1);
 }
 
-static int str9xpec_info(struct flash_bank *bank, char *buf, int buf_size)
+static int get_str9xpec_info(struct flash_bank *bank, char *buf, int buf_size)
 {
 	snprintf(buf, buf_size, "str9xpec flash driver info");
 	return ERROR_OK;
@@ -1252,5 +1302,5 @@ struct flash_driver str9xpec_flash = {
 	.auto_probe = str9xpec_probe,
 	.erase_check = str9xpec_erase_check,
 	.protect_check = str9xpec_protect_check,
-	.info = str9xpec_info,
+	.info = get_str9xpec_info,
 };