X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=doc%2Fopenocd.texi;h=479bf34ecbad1b72d7c9afe21fe1ac19647ac316;hb=b13055069c12fe0f8d60777b37f0df39d883e359;hp=bbb907558950b58bd80f7905c866632f6f82f1fb;hpb=85ba2dc4c6ab4c91f4461c2853660cc2cb9e2623;p=openocd.git diff --git a/doc/openocd.texi b/doc/openocd.texi index bbb9075589..479bf34ecb 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -1802,10 +1802,11 @@ displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP wi The SMP behaviour can be disabled/enabled dynamically. On cortex_a following command have been implemented. @itemize @bullet -@item cortex_a smp_on : enable SMP mode, behaviour is as described above. -@item cortex_a smp_off : disable SMP mode, the current target is the one +@item cortex_a smp on : enable SMP mode, behaviour is as described above. +@item cortex_a smp off : disable SMP mode, the current target is the one displayed in the GDB session, only this target is now controlled by GDB session. This behaviour is useful during system boot up. +@item cortex_a smp : display current SMP mode. @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see following example. @end itemize @@ -2513,7 +2514,7 @@ and are not restricted to containing only decimal digits.) @deffn {Config Command} {ftdi_location} -[.]... @emph{DEPRECATED -- avoid using this. -Use the @xref{adapter_usb_location, adapter usb location} command instead.} +Use the command @ref{adapter_usb_location,,adapter usb location} instead.} Specifies the physical USB port of the adapter to use. The path roots at @var{bus} and walks down the physical ports, with each @@ -3894,10 +3895,14 @@ devices do not set the ack bit until sometime later. @section Other TAP commands +@deffn Command {jtag cget} dotted.name @option{-idcode} +Get the value of the IDCODE found in hardware. +@end deffn + @deffn Command {jtag cget} dotted.name @option{-event} event_name @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler At this writing this TAP attribute -mechanism is used only for event handling. +mechanism is limited and used mostly for event handling. (It is not a direct analogue of the @code{cget}/@code{configure} mechanism for debugger targets.) See the next section for information about the available events. @@ -4366,6 +4371,7 @@ compact Thumb2 instruction set. The current implementation supports eSi-32xx cores. @item @code{fa526} -- resembles arm920 (w/o Thumb) @item @code{feroceon} -- resembles arm926 +@item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without a CPU, through which bus read and write cycles can be generated; it may be useful for working with non-CPU hardware behind an AP or during development of support for new CPUs. @item @code{mips_m4k} -- a MIPS core @item @code{xscale} -- this is actually an architecture, not a CPU type. It is based on the ARMv5 architecture. @@ -4374,14 +4380,14 @@ The current implementation supports three JTAG TAP cores: @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs, allowing access to physical memory addresses independently of CPU cores. @itemize @minus -@item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag}) +@item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag}) @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf}) @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf}) @end itemize And two debug interfaces cores: @itemize @minus -@item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys}) -@item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface}) +@item @code{Advanced debug interface} (See: @url{http://opencores.org/project@comma{}adv_debug_sys}) +@item @code{SoC Debug Interface} (See: @url{http://opencores.org/project@comma{}dbg_interface}) @end itemize @end itemize @end deffn @@ -8940,12 +8946,8 @@ Initialize core debug Enables debug by unlocking the Software Lock and clearing sticky powerdown indications @end deffn -@deffn Command {cortex_a smp_off} -Disable SMP mode -@end deffn - -@deffn Command {cortex_a smp_on} -Enable SMP mode +@deffn Command {cortex_a smp} [on|off] +Display/set the current SMP mode @end deffn @deffn Command {cortex_a smp_gdb} [core_id] @@ -9076,7 +9078,7 @@ Enable or disable trace output for all ITM stimulus ports. @subsection Cortex-M specific commands @cindex Cortex-M -@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}) +@deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly}) Control masking (disabling) interrupts during target step/resume. The @option{auto} option handles interrupts during stepping in a way that they @@ -9086,6 +9088,11 @@ the next instruction where the core was halted. After the step interrupts are enabled again. If the interrupt handlers don't complete within 500ms, the step command leaves with the core running. +The @option{steponly} option disables interrupts during single-stepping but +enables them during normal execution. This can be used as a partial workaround +for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with +FPU (AT611) Software Developer Errata Notice" from ARM for further details. + Note that a free hardware (FPB) breakpoint is required for the @option{auto} option. If no breakpoint is available at the time of the step, then the step is taken with interrupts enabled, i.e. the same way the @option{off} option @@ -9156,8 +9163,8 @@ target code relies on. In a configuration file, the command would typically be c However, normally it is not necessary to use the command at all. @end deffn -@deffn Command {aarch64 smp_on|smp_off} -Enable and disable SMP handling. The state of SMP handling influences the way targets in an SMP group +@deffn Command {aarch64 smp} [on|off] +Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP group. With SMP handling disabled, all targets need to be treated individually. @@ -9466,6 +9473,14 @@ command can be used if OpenOCD gets this wrong, or a target implements custom CSRs. @end deffn +@deffn Command {riscv expose_custom} n0[-m0][,n1[-m1]]... +The RISC-V Debug Specification allows targets to expose custom registers +through abstract commands. (See Section 3.5.1.1 in that document.) This command +configures a list of inclusive ranges of those registers to expose. Number 0 +indicates the first custom register, whose abstract command number is 0xc000. +This command must be executed before `init`. +@end deffn + @deffn Command {riscv set_command_timeout_sec} [seconds] Set the wall-clock timeout (in seconds) for individual commands. The default should work fine for all but the slowest targets (eg. simulators). @@ -9486,6 +9501,17 @@ When on, prefer to use System Bus Access to access memory. When off, prefer to use the Program Buffer to access memory. @end deffn +@deffn Command {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value] +Set the IR value for the specified JTAG register. This is useful, for +example, when using the existing JTAG interface on a Xilinx FPGA by +way of BSCANE2 primitives that only permit a limited selection of IR +values. + +When utilizing version 0.11 of the RISC-V Debug Specification, +@option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL +and DBUS registers, respectively. +@end deffn + @subsection RISC-V Authentication Commands The following commands can be used to authenticate to a RISC-V system. Eg. a