X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=doc%2Fopenocd.texi;h=10d40570123b2b9355fd44c4676693fd240a1ebd;hb=4457800afe9ab2e1e7e466570b52a764cbd22574;hp=f2cbfa4217d2e3985ec25b622e20c781fd15c2b9;hpb=20ff917e29cd2b14b01a3491b302e0310d620ebe;p=openocd.git

diff --git a/doc/openocd.texi b/doc/openocd.texi
index f2cbfa4217..10d4057012 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -12,6 +12,7 @@
 
 @copying
 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
+Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
 @quotation
 Permission is granted to copy, distribute and/or modify this document
 under the terms of the GNU Free Documentation License, Version 1.2 or
@@ -95,6 +96,12 @@ The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
 @chapter Building
 @cindex building OpenOCD
 
+If you are interested in getting actual work done rather than building
+OpenOCD, then check if your interface supplier provides binaries for
+you. Chances are that that binary is from some SVN version that is more
+stable than SVN trunk where bleeding edge development takes place.
+
+
 You can download the current SVN version with SVN client of your choice from the
 following repositories:
 
@@ -256,6 +263,11 @@ OpenOCD command line using the @option{-c} command line switch.
 @item @b{telnet_port} <@var{number}>
 @cindex telnet_port
 Port on which to listen for incoming telnet connections 
+@item @b{tcl_port} <@var{number}>
+@cindex tcl_port
+Port on which to listen for incoming TCL syntax. This port is intended as
+a simplified RPC connection that can be used by clients to issue commands
+and get the output from the TCL engine.
 @item @b{gdb_port} <@var{number}>
 @cindex gdb_port
 First port on which to listen for incoming GDB connections. The GDB port for the
@@ -286,11 +298,6 @@ Default behaviour is <@var{enable}>
 Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
 vFlash packet is received.
 Default behaviour is <@var{enable}>
- at item @b{tcl_port} <@var{number}>
- at cindex tcl_port
-Port on which to listen for incoming TCL syntax. This port is intended as
-a simplified RPC connection that can be used by clients to issue commands
-and get the output from the TCL engine.
 @end itemize
 
 @section JTAG interface configuration
@@ -408,8 +415,7 @@ How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
 starting new JTAG operations. 
 @item @b{jtag_ntrst_delay} <@var{ms}>
 @cindex jtag_ntrst_delay
-How long (in milliseconds) OpenOCD should wait after deasserting nTRST before
-starting new JTAG operations. 
+Same @b{jtag_nsrst_delay}, but for nTRST  
 
 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
 or on-chip features) keep a reset line asserted for some time after the external reset
@@ -436,13 +442,20 @@ Currently supported cables are
 @cindex wiggler
 The original Wiggler layout, also supported by several clones, such
 as the Olimex ARM-JTAG
+@item @b{wiggler2}
+@cindex wiggler2
+Same as original wiggler except an led is fitted on D5.
+@item @b{wiggler_ntrst_inverted}
+@cindex wiggler_ntrst_inverted
+Same as original wiggler except TRST is inverted.
 @item @b{old_amt_wiggler}
 @cindex old_amt_wiggler
 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
 version available from the website uses the original Wiggler layout ('@var{wiggler}')
 @item @b{chameleon}
 @cindex chameleon
-The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to program the Chameleon itself, not a connected target.
+The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
+program the Chameleon itself, not a connected target.
 @item @b{dlc5}
 @cindex dlc5
 The Xilinx Parallel cable III.
@@ -453,7 +466,14 @@ This is also the layout used by the HollyGates design
 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
 @item @b{flashlink}
 @cindex flashlink
-The ST Parallel cable. 
+The ST Parallel cable.
+@item @b{arm-jtag}
+@cindex arm-jtag
+Same as original wiggler except SRST and TRST connections reversed and
+TRST is also inverted.
+@item @b{altium}
+@cindex altium
+Altium Universal JTAG cable.
 @end itemize
 @item @b{parport_write_on_exit} <@var{on|off}>
 @cindex parport_write_on_exit
@@ -688,6 +708,12 @@ stellaris flash plugin only require the @var{target#}.
 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
 stm32x flash plugin only require the @var{target#}. 
 
+@subsection aduc702x options
+@cindex aduc702x options
+
+@b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
+aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
+
 @node Target library
 @chapter Target library
 @cindex Target library
@@ -1054,15 +1080,6 @@ The target is resumed in the currently set @option{core_mode}.
 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
 ARM920t or ARM926EJ-S.
 @itemize @bullet
-@item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
-@cindex arm7_9 sw_bkpts
-Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
-one of the watchpoint registers to implement software breakpoints. Disabling
-SW Bkpts frees that register again. 
-@item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
-@cindex arm7_9 force_hw_bkpts
-When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
-breakpoints are turned into hardware breakpoints.
 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
 @cindex arm7_9 dbgrq
 Enable use of the DBGRQ bit to force entry into debug mode. This should be
@@ -1277,6 +1294,11 @@ to debug remote targets.
 
 @section Connecting to gdb
 @cindex Connecting to gdb
+Use GDB 6.7 or newer with OpenOCD if you run into trouble. For instance 6.3 has a 
+known bug where it produces bogus memory access errors, which has since
+been fixed: look up 1836 in http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb 
+
+
 A connection is typically started as follows:
 @smallexample
 target remote localhost:3333
@@ -1314,7 +1336,7 @@ working area.
 
 Informing gdb of the memory map of the target will enable gdb to protect any
 flash area of the target and use hardware breakpoints by default. This means
-that the OpenOCD option @option{arm7_9 force_hw_bkpts} is not required when
+that the OpenOCD option @option{gdb_breakpoint_override} is not required when
 using a memory map.
 
 To view the configured memory map in gdb, use the gdb command @option{info mem}
@@ -1432,6 +1454,10 @@ Certain OpenOCD commands have been deprecated/removed during the various revisio
 @item @b{load_binary}
 @cindex load_binary
 use @option{load_image} command with same args
+@item @b{target}
+@cindex target
+@option{target} no longer take the reset_init, reset_run, run_and_halt, run_and_init. The @option{reset} command
+always does a @option{reset run} when passed no arguments.
 @item @b{dump_binary}
 @cindex dump_binary
 use @option{dump_image} command with same args
@@ -1455,6 +1481,14 @@ use @option{flash write_image} command passing @option{erase} as the first param
 this config option has been removed, simply adding @option{init} and @option{reset halt} to
 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
 and @option{target cortex_m3 little reset_halt 0}.
+@item @b{arm7_9 sw_bkpts}
+@cindex arm7_9 sw_bkpts
+On by default. See also @option{gdb_breakpoint_override}. 
+@item @b{arm7_9 force_hw_bkpts}
+@cindex arm7_9 force_hw_bkpts
+Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
+for flash if the gdb memory map has been set up(default when flash is declared in
+target configuration).
 @item @b{run_and_halt_time}
 @cindex run_and_halt_time
 This command has been removed for simpler reset behaviour, it can be simulated with the
@@ -1482,11 +1516,7 @@ arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not e
 
 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
-software breakpoints consume one of the two available hardware breakpoints,
-and are therefore disabled by default. If your code is running from RAM, you
-can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
-your code resides in Flash, you can't use software breakpoints, but you can force
-OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
+software breakpoints consume one of the two available hardware breakpoints.  
 
 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
 and works sometimes fine.