X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=NEWS;h=c5811bce5b35545f0e11acde904f49749714abdf;hb=46ed068bacec3c40aa543e78e99b51e30aacf15b;hp=a0bf43c21ff0e120ed915bc5185b1dc37d1b56b1;hpb=49036463dbebcd4c5722f89b86dc6cec777bab0f;p=openocd.git

diff --git a/NEWS b/NEWS
index a0bf43c21f..c5811bce5b 100644
--- a/NEWS
+++ b/NEWS
@@ -10,10 +10,20 @@ Boundary Scan:
 Target Layer:
 	ARM
 		- renamed "armv4_5" command prefix as "arm"
+		- recognize TrustZone "Secure Monitor" mode
+		- "arm regs" command output changed
+		- register names use "sp" not "r13"
 	ARM11
 		- Preliminary ETM and ETB hookup
 		- accelerated "flash erase_check"
 		- accelerated GDB memory checksum
+		- support "arm regs" command
+		- can access all core modes and registers
+	Cortex-A8
+		- support "arm regs" command
+		- can access all core modes and registers
+	Cortex-M3
+		- Exposed DWT registers like cycle counter
 
 Flash Layer:
 	'flash bank' and 'nand device' take <bank_name> as first argument.