X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Fferoceon.c;h=4a6c6dcf0be4fadabcc050290264890e90ead1d3;hb=5fbf4d4cc3f67ec8b2fb3d8a789117583a84e1a1;hp=f12e4e450628e1c8e62f73bc11158e333594da5e;hpb=d0e763ac7ef6aa17b17bd00ccdfbccfb4eacda69;p=openocd.git

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index f12e4e4506..4a6c6dcf0b 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -460,7 +460,7 @@ static int feroceon_examine_debug_reason(struct target *target)
 }
 
 static int feroceon_bulk_write_memory(struct target *target,
-		uint32_t address, uint32_t count, const uint8_t *buffer)
+		target_addr_t address, uint32_t count, const uint8_t *buffer)
 {
 	int retval;
 	struct arm *arm = target->arch_info;
@@ -532,8 +532,8 @@ static int feroceon_bulk_write_memory(struct target *target,
 
 	/* set up target address in r0 */
 	buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address);
-	arm->core_cache->reg_list[0].valid = 1;
-	arm->core_cache->reg_list[0].dirty = 1;
+	arm->core_cache->reg_list[0].valid = true;
+	arm->core_cache->reg_list[0].dirty = true;
 	arm->core_state = ARM_STATE_ARM;
 
 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
@@ -565,7 +565,7 @@ static int feroceon_bulk_write_memory(struct target *target,
 			buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32);
 		if (endaddress != address + count*4) {
 			LOG_ERROR("DCC write failed,"
-				" expected end address 0x%08" PRIx32
+				" expected end address 0x%08" TARGET_PRIxADDR
 				" got 0x%0" PRIx32 "",
 				address + count*4, endaddress);
 			retval = ERROR_FAIL;
@@ -575,12 +575,12 @@ static int feroceon_bulk_write_memory(struct target *target,
 	/* restore target state */
 	for (i = 0; i <= 5; i++) {
 		buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]);
-		arm->core_cache->reg_list[i].valid = 1;
-		arm->core_cache->reg_list[i].dirty = 1;
+		arm->core_cache->reg_list[i].valid = true;
+		arm->core_cache->reg_list[i].dirty = true;
 	}
 	buf_set_u32(arm->pc->value, 0, 32, save[i]);
-	arm->pc->valid = 1;
-	arm->pc->dirty = 1;
+	arm->pc->valid = true;
+	arm->pc->dirty = true;
 	arm->core_state = core_state;
 
 	return retval;
@@ -710,6 +710,7 @@ struct target_type feroceon_target = {
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm926ejs_soft_reset_halt,
 
+	.get_gdb_arch = arm_get_gdb_arch,
 	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
@@ -747,6 +748,7 @@ struct target_type dragonite_target = {
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
+	.get_gdb_arch = arm_get_gdb_arch,
 	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,