X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Fcortex_m3.c;h=d617817d14c8c17c8d85a39fb4d80a23bfd9bcdc;hb=42ef503d37b18d907da16d26e99167566d5aabd1;hp=e157805046adc3e60cb9d5f9967edd3ed368b1e7;hpb=da739aa25733b5a252a2b0b8ad76a3dc886f1132;p=openocd.git diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index e157805046..d617817d14 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -56,12 +56,6 @@ extern uint8_t armv7m_gdb_dummy_cpsr_value[]; extern reg_t armv7m_gdb_dummy_cpsr_reg; #endif -static int cortex_m3_has_mmu(struct target_s *target, bool *has_mmu) -{ - *has_mmu = false; - return ERROR_OK; -} - static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, int regnum) { @@ -1578,7 +1572,7 @@ fail1: *register_get_last_cache_p(&target->reg_cache) = cache; cm3->dwt_cache = cache; - LOG_INFO("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s", + LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s", dwtcr, cm3->dwt_num_comp, (dwtcr & (0xf << 24)) ? " only" : "/trigger"); @@ -1714,7 +1708,7 @@ static int cortex_m3_handle_target_request(void *priv) } static int cortex_m3_init_arch_info(target_t *target, - cortex_m3_common_t *cortex_m3, jtag_tap_t *tap) + cortex_m3_common_t *cortex_m3, struct jtag_tap *tap) { int retval; struct armv7m_common_s *armv7m = &cortex_m3->armv7m; @@ -1787,9 +1781,7 @@ static int cortex_m3_verify_pointer(struct command_context_s *cmd_ctx, * that *only* Thumb2 disassembly matters. There are also some small * additions to Thumb2 that are specific to ARMv7-M. */ -static int -handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_cortex_m3_disassemble_command) { int retval; target_t *target = get_current_target(cmd_ctx); @@ -1841,9 +1833,7 @@ static const struct { { "reset", VC_CORERESET, }, }; -static int -handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx, - char *cmd, char **argv, int argc) +COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) { target_t *target = get_current_target(cmd_ctx); struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); @@ -1863,24 +1853,24 @@ handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx, unsigned catch = 0; if (argc == 1) { - if (strcmp(argv[0], "all") == 0) { + if (strcmp(args[0], "all") == 0) { catch = VC_HARDERR | VC_INTERR | VC_BUSERR | VC_STATERR | VC_CHKERR | VC_NOCPERR | VC_MMERR | VC_CORERESET; goto write; - } else if (strcmp(argv[0], "none") == 0) { + } else if (strcmp(args[0], "none") == 0) { goto write; } } while (argc-- > 0) { for (i = 0; i < ARRAY_SIZE(vec_ids); i++) { - if (strcmp(argv[argc], vec_ids[i].name) != 0) + if (strcmp(args[argc], vec_ids[i].name) != 0) continue; catch |= vec_ids[i].mask; break; } if (i == ARRAY_SIZE(vec_ids)) { - LOG_ERROR("No CM3 vector '%s'", argv[argc]); + LOG_ERROR("No CM3 vector '%s'", args[argc]); return ERROR_INVALID_ARGUMENTS; } } @@ -1900,9 +1890,7 @@ write: return ERROR_OK; } -static int -handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command) { target_t *target = get_current_target(cmd_ctx); struct cortex_m3_common_s *cortex_m3 = target_to_cm3(target); @@ -1914,7 +1902,7 @@ handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } @@ -1998,6 +1986,5 @@ target_type_t cortexm3_target = .register_commands = cortex_m3_register_commands, .target_create = cortex_m3_target_create, .init_target = cortex_m3_init_target, - .has_mmu = cortex_m3_has_mmu, .examine = cortex_m3_examine, };