X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farmv7m.h;h=6c751332b4f1f3cfd5dfcea49849f492b08a858f;hb=aea6815462d3302f7f8b6576f59320d5f5985642;hp=ebbf437fccaa3b5e421b3534c4dacfe421742fa0;hpb=cab29a63de935871135a6ee0ed9d29d5edea0f27;p=openocd.git

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index ebbf437fcc..6c751332b4 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -5,6 +5,9 @@
  *   Copyright (C) 2006 by Magnus Lundin                                   *
  *   lundin@mlu.mine.nu                                                    *
  *                                                                         *
+ *   Copyright (C) 2008 by Spencer Oliver                                  *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -23,9 +26,7 @@
 #ifndef ARMV7M_COMMON_H
 #define ARMV7M_COMMON_H
 
-#include "register.h"
-#include "target.h"
-#include "arm_jtag.h"
+#include "arm_adi_v5.h"
 
 /* define for enabling armv7 gdb workarounds */
 #if 1
@@ -75,16 +76,16 @@ typedef struct armv7m_common_s
 	reg_cache_t *core_cache;
 	enum armv7m_mode core_mode;
 	int exception_number;
+	swjdp_common_t swjdp_info;
+
 	
 	/* Direct processor core register read and writes */
-	int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
-	int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value);
+	int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
+	int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
 	/* register cache to processor synchronization */
 	int (*read_core_reg)(struct target_s *target, int num);
 	int (*write_core_reg)(struct target_s *target, int num);
 	
-	arm_jtag_t jtag_info;
-
 	int (*examine_debug_reason)(target_t *target);
 	void (*pre_debug_entry)(target_t *target);
 	void (*post_debug_entry)(target_t *target);
@@ -104,7 +105,7 @@ typedef struct armv7m_algorithm_s
 
 typedef struct armv7m_core_reg_s
 {
-	u32 num;
+	uint32_t num;
 	enum armv7m_regtype type;
 	enum armv7m_mode mode;
 	target_t *target;
@@ -117,18 +118,18 @@ extern int armv7m_mode_to_number(enum armv7m_mode mode);
 
 extern int armv7m_arch_state(struct target_s *target);
 extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
-extern int armv7m_invalidate_core_regs(target_t *target);
 
 extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
 extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
 
-extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
+extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
 
 extern int armv7m_invalidate_core_regs(target_t *target);
 
 extern int armv7m_restore_context(target_t *target);
 
-extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
+extern int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
+extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank);
 
 /* Thumb mode instructions
  */
@@ -137,13 +138,13 @@ extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 coun
  * Rd: destination register
  * SYSm: source special register
  */
-#define ARMV7M_T_MRS(Rd, SYSm)	((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16)) 
+#define ARMV7M_T_MRS(Rd, SYSm)	((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) 
 
 /* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
  * Rd: source register
  * SYSm: destination special register
  */
-#define ARMV7M_T_MSR(SYSm, Rn)	((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16)) 
+#define ARMV7M_T_MSR(SYSm, Rn)	((0xF380 | ( Rn << 8 )) | ((0x8800 | SYSm) << 16)) 
 
 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK 
  * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
@@ -152,8 +153,8 @@ extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 coun
  */
 #define I_FLAG 2
 #define F_FLAG 1  
-#define ARMV7M_T_CPSID(IF)	((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16)) 
-#define ARMV7M_T_CPSIE(IF)	((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16)) 
+#define ARMV7M_T_CPSID(IF)	((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16)) 
+#define ARMV7M_T_CPSIE(IF)	((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16)) 
 
 /* Breakpoint (Thumb mode) v5 onwards
  * Im: immediate value used by debugger