X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farmv7a.h;h=575363d1fdc17f8b1feaa5e0bd8466caaa30c66e;hb=13288a44bee0aa26067cb51c262b82a12b61699f;hp=f93245634adb3bd147f9f076b4c1cfa1f779af06;hpb=44ef0327dd97c1893afc63cd7fd8025cb1b57827;p=openocd.git

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index f93245634a..575363d1fd 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -16,6 +16,7 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifndef ARMV7A_H
 #define ARMV7A_H
 
@@ -25,12 +26,10 @@
 #include "armv4_5_cache.h"
 #include "arm_dpm.h"
 
-enum
-{
+enum {
 	ARM_PC  = 15,
 	ARM_CPSR = 16
-}
-;
+};
 
 #define ARMV7_COMMON_MAGIC 0x0A450999
 
@@ -43,10 +42,53 @@ enum
 #define V2POWPW  5
 #define V2POWUR  6
 #define V2POWUW  7
+/*   L210/L220 cache controller support */
+struct armv7a_l2x_cache {
+	uint32_t base;
+	uint32_t way;
+};
 
-struct armv7a_common
-{
-	struct arm armv4_5_common;
+struct armv7a_cachesize {
+	uint32_t level_num;
+	/*  cache dimensionning */
+	uint32_t linelen;
+	uint32_t associativity;
+	uint32_t nsets;
+	uint32_t cachesize;
+	/* info for set way operation on cache */
+	uint32_t index;
+	uint32_t index_shift;
+	uint32_t way;
+	uint32_t way_shift;
+};
+
+struct armv7a_cache_common {
+	int ctype;
+	struct armv7a_cachesize d_u_size;	/* data cache */
+	struct armv7a_cachesize i_size;		/* instruction cache */
+	int i_cache_enabled;
+	int d_u_cache_enabled;
+	/* l2 external unified cache if some */
+	void *l2_cache;
+	int (*flush_all_data_cache)(struct target *target);
+	int (*display_cache_info)(struct command_context *cmd_ctx,
+			struct armv7a_cache_common *armv7a_cache);
+};
+
+struct armv7a_mmu_common {
+	/* following field mmu working way */
+	int32_t ttbr1_used; /*  -1 not initialized, 0 no ttbr1 1 ttbr1 used and  */
+	uint32_t ttbr0_mask;/*  masked to be used  */
+	uint32_t os_border;
+
+	int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
+			uint32_t count, uint8_t *buffer);
+	struct armv7a_cache_common armv7a_cache;
+	uint32_t mmu_enabled;
+};
+
+struct armv7a_common {
+	struct arm arm;
 	int common_magic;
 	struct reg_cache *core_cache;
 
@@ -57,9 +99,15 @@ struct armv7a_common
 	uint32_t debug_base;
 	uint8_t debug_ap;
 	uint8_t memory_ap;
+	bool memory_ap_available;
+	/* mdir */
+	uint8_t multi_processor_system;
+	uint8_t cluster_id;
+	uint8_t cpu_id;
+	bool is_armv7r;
 
-	/* Cache and Memory Management Unit */
-	struct armv4_5_mmu_common armv4_5_mmu;
+	/* cache specific to V7 Memory Management Unit compatible with v4_5*/
+	struct armv7a_mmu_common armv7a_mmu;
 
 	int (*examine_debug_reason)(struct target *target);
 	int (*post_debug_entry)(struct target *target);
@@ -70,8 +118,7 @@ struct armv7a_common
 static inline struct armv7a_common *
 target_to_armv7a(struct target *target)
 {
-	return container_of(target->arch_info, struct armv7a_common,
-			armv4_5_common);
+	return container_of(target->arch_info, struct armv7a_common, arm);
 }
 
 /* register offsets from armv7a.debug_base */
@@ -112,9 +159,14 @@ target_to_armv7a(struct target *target)
 #define CPUDBG_AUTHSTATUS	0xFB8
 
 int armv7a_arch_state(struct target *target);
-struct reg_cache *armv7a_build_reg_cache(struct target *target,
-		struct armv7a_common *armv7a_common);
+int armv7a_identify_cache(struct target *target);
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
+int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
+		uint32_t *val, int meminfo);
+int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val);
+
+int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
+		struct armv7a_cache_common *armv7a_cache);
 
 extern const struct command_registration armv7a_command_handlers[];