X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farm_dpm.h;h=82707822b1f90cf576533568305ebf98ba1d2584;hb=996ff5bcfc402227ac2f28601e931f30b62e393f;hp=f8d124813658a0ffe4a4c9293f99dc67963663e9;hpb=79c4c22e1570cf0d73bacb4d292951e614d0ab2f;p=openocd.git

diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index f8d1248136..82707822b1 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -62,29 +62,29 @@ struct arm_dpm {
 	uint64_t didr;
 
 	/** Invoke before a series of instruction operations */
-	int (*prepare)(struct arm_dpm *);
+	int (*prepare)(struct arm_dpm *dpm);
 
 	/** Invoke after a series of instruction operations */
-	int (*finish)(struct arm_dpm *);
+	int (*finish)(struct arm_dpm *dpm);
 
 	/** Runs one instruction. */
-	int (*instr_execute)(struct arm_dpm *, uint32_t opcode);
+	int (*instr_execute)(struct arm_dpm *dpm, uint32_t opcode);
 
 	/* WRITE TO CPU */
 
 	/** Runs one instruction, writing data to DCC before execution. */
-	int (*instr_write_data_dcc)(struct arm_dpm *,
+	int (*instr_write_data_dcc)(struct arm_dpm *dpm,
 			uint32_t opcode, uint32_t data);
 
-	int (*instr_write_data_dcc_64)(struct arm_dpm *,
+	int (*instr_write_data_dcc_64)(struct arm_dpm *dpm,
 			uint32_t opcode, uint64_t data);
 
 	/** Runs one instruction, writing data to R0 before execution. */
-	int (*instr_write_data_r0)(struct arm_dpm *,
+	int (*instr_write_data_r0)(struct arm_dpm *dpm,
 			uint32_t opcode, uint32_t data);
 
 	/** Runs one instruction, writing data to R0 before execution. */
-	int (*instr_write_data_r0_64)(struct arm_dpm *,
+	int (*instr_write_data_r0_64)(struct arm_dpm *dpm,
 			uint32_t opcode, uint64_t data);
 
 	/** Optional core-specific operation invoked after CPSR writes. */
@@ -93,17 +93,17 @@ struct arm_dpm {
 	/* READ FROM CPU */
 
 	/** Runs one instruction, reading data from dcc after execution. */
-	int (*instr_read_data_dcc)(struct arm_dpm *,
+	int (*instr_read_data_dcc)(struct arm_dpm *dpm,
 			uint32_t opcode, uint32_t *data);
 
-	int (*instr_read_data_dcc_64)(struct arm_dpm *,
+	int (*instr_read_data_dcc_64)(struct arm_dpm *dpm,
 			uint32_t opcode, uint64_t *data);
 
 	/** Runs one instruction, reading data from r0 after execution. */
-	int (*instr_read_data_r0)(struct arm_dpm *,
+	int (*instr_read_data_r0)(struct arm_dpm *dpm,
 			uint32_t opcode, uint32_t *data);
 
-	int (*instr_read_data_r0_64)(struct arm_dpm *,
+	int (*instr_read_data_r0_64)(struct arm_dpm *dpm,
 			uint32_t opcode, uint64_t *data);
 
 	struct reg *(*arm_reg_current)(struct arm *arm,
@@ -117,7 +117,7 @@ struct arm_dpm {
 	 * must currently be disabled.  Indices 0..15 are used for
 	 * breakpoints; indices 16..31 are for watchpoints.
 	 */
-	int (*bpwp_enable)(struct arm_dpm *, unsigned index_value,
+	int (*bpwp_enable)(struct arm_dpm *dpm, unsigned index_value,
 			uint32_t addr, uint32_t control);
 
 	/**
@@ -125,7 +125,7 @@ struct arm_dpm {
 	 * hardware control registers.  Indices are the same ones
 	 * accepted by bpwp_enable().
 	 */
-	int (*bpwp_disable)(struct arm_dpm *, unsigned index_value);
+	int (*bpwp_disable)(struct arm_dpm *dpm, unsigned index_value);
 
 	/* The breakpoint and watchpoint arrays are private to the
 	 * DPM infrastructure.  There are nbp indices in the dbp
@@ -152,12 +152,13 @@ struct arm_dpm {
 int arm_dpm_setup(struct arm_dpm *dpm);
 int arm_dpm_initialize(struct arm_dpm *dpm);
 
-int arm_dpm_read_current_registers(struct arm_dpm *);
-int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
+int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum);
+int arm_dpm_read_current_registers(struct arm_dpm *dpm);
+int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
 
-int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
+int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
 
-void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
+void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar);
 
 /* DSCR bits; see ARMv7a arch spec section C10.3.1.
  * Not all v7 bits are valid in v6.