X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farm7_9_common.c;h=2a149425be613df70eb6cf9e90aa434f43b59f92;hb=1aa854684de1827edd3b605fc64a78a498f2358a;hp=ee814ba928fbee80ec7464cfb55af06a717b7450;hpb=2e01a1ad1930aabb9e3bc7a0e3eb98b2b3331b1c;p=openocd.git diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index ee814ba928..2a149425be 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -186,17 +186,33 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { if (breakpoint->length == 4) { + u32 verify = 0xffffffff; /* keep the original instruction in target endianness */ target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr); /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */ target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt); + + target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify); + if (verify != arm7_9->arm_bkpt) + { + ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address); + return ERROR_OK; + } } else { + u16 verify = 0xffff; /* keep the original instruction in target endianness */ target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */ target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt); + + target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify); + if (verify != arm7_9->thumb_bkpt) + { + ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address); + return ERROR_OK; + } } breakpoint->set = 1; } @@ -638,6 +654,9 @@ int arm7_9_handle_target_request(void *priv) arm_jtag_t *jtag_info = &arm7_9->jtag_info; reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; + if (!target->dbg_msg_enabled) + return ERROR_OK; + if (target->state == TARGET_RUNNING) { /* read DCC control register */ @@ -657,7 +676,7 @@ int arm7_9_handle_target_request(void *priv) return ERROR_OK; } -enum target_state arm7_9_poll(target_t *target) +int arm7_9_poll(target_t *target) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -673,24 +692,15 @@ enum target_state arm7_9_poll(target_t *target) embeddedice_read_reg(dbg_stat); if ((retval = jtag_execute_queue()) != ERROR_OK) { - switch (retval) - { - case ERROR_JTAG_QUEUE_FAILED: - ERROR("JTAG queue failed while reading EmbeddedICE status register"); - exit(-1); - break; - default: - break; - } + return retval; } if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)) { DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32)); - if ((target->state == TARGET_UNKNOWN)) + if (target->state == TARGET_UNKNOWN) { - WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming"); - target->state = TARGET_RUNNING; + WARNING("DBGACK set while target was in unknown state. Reset or initialize target."); } if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { @@ -708,14 +718,18 @@ enum target_state arm7_9_poll(target_t *target) target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } - } + if (target->state != TARGET_HALTED) + { + WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state); + } + } else { if (target->state != TARGET_DEBUG_RUNNING) target->state = TARGET_RUNNING; } - return target->state; + return ERROR_OK; } int arm7_9_assert_reset(target_t *target) @@ -1143,8 +1157,8 @@ int arm7_9_debug_entry(target_t *target) } /* r0 and r15 (pc) have to be restored later */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid; if ((retval = jtag->execute_queue()) != ERROR_OK) return retval; @@ -1288,7 +1302,6 @@ int arm7_9_restore_context(target_t *target) else { ERROR("BUG: dirty register '%s', but no valid data", reg->name); - exit(-1); } } } @@ -1445,6 +1458,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ arm7_9_common_t *arm7_9 = armv4_5->arch_info; breakpoint_t *breakpoint = target->breakpoints; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + int err; DEBUG("-"); @@ -1492,14 +1506,21 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0); embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size)); - arm7_9_execute_sys_speed(target); + err = arm7_9_execute_sys_speed(target); DEBUG("disable single-step"); arm7_9->disable_single_step(target); - + + if (err != ERROR_OK) + { + arm7_9_set_breakpoint(target, breakpoint); + target->state = TARGET_UNKNOWN; + return err; + } + arm7_9_debug_entry(target); DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - + DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); arm7_9_set_breakpoint(target, breakpoint); } @@ -1595,6 +1616,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; breakpoint_t *breakpoint = NULL; + int err; if (target->state != TARGET_HALTED) { @@ -1633,22 +1655,25 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - arm7_9_execute_sys_speed(target); + err = arm7_9_execute_sys_speed(target); arm7_9->disable_single_step(target); /* registers are now invalid */ armv4_5_invalidate_core_regs(target); - arm7_9_debug_entry(target); + if (err != ERROR_OK) + { + target->state = TARGET_UNKNOWN; + } else { + arm7_9_debug_entry(target); + target_call_event_callbacks(target, TARGET_EVENT_HALTED); + DEBUG("target stepped"); + } - target_call_event_callbacks(target, TARGET_EVENT_HALTED); - if (breakpoint) arm7_9_set_breakpoint(target, breakpoint); - DEBUG("target stepped"); - - return ERROR_OK; + return err; } @@ -1905,13 +1930,13 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count } for (i=0; i<=last_reg; i++) - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); if ((retval = jtag_execute_queue()) != ERROR_OK) { ERROR("JTAG error while reading cpsr"); - exit(-1); + return ERROR_TARGET_DATA_ABORT; } if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT)) @@ -1940,7 +1965,9 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun int retval; int last_reg = 0; +#ifdef _DEBUG_ARM7_9_ DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); +#endif if (target->state != TARGET_HALTED) { @@ -2070,13 +2097,13 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun embeddedice_store_reg(dbg_ctrl); for (i=0; i<=last_reg; i++) - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); if ((retval = jtag_execute_queue()) != ERROR_OK) { ERROR("JTAG error while reading cpsr"); - exit(-1); + return ERROR_TARGET_DATA_ABORT; } if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))