X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farm11.c;h=5e7327583e8167276b632828222af0a5d5fe43b1;hb=d6c8945662e6027f6ba12d73bac2473088672db5;hp=b30e5181a87db7f820430aa47efb50e54e8ea918;hpb=817bf743023de7fea901e89157da57b90c7c326c;p=openocd.git diff --git a/src/target/arm11.c b/src/target/arm11.c index b30e5181a8..5e7327583e 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -26,12 +26,14 @@ #include "config.h" #endif -#include "arm11.h" +#include "etm.h" +#include "breakpoints.h" #include "arm11_dbgtap.h" -#include "armv4_5.h" #include "arm_simulator.h" #include "time_support.h" #include "target_type.h" +#include "algorithm.h" +#include "register.h" #if 0 @@ -56,8 +58,6 @@ static uint32_t arm11_vcr = 0; static bool arm11_config_step_irq_enable = false; static bool arm11_config_hardware_step = false; -static int arm11_regs_arch_type = -1; - enum arm11_regtype { ARM11_REGISTER_CORE, @@ -246,38 +246,6 @@ enum arm11_regcache_ids #define ARM11_GDB_REGISTER_COUNT 26 -/* FIXME these are *identical* to the ARMv4_5 dummies ... except - * for their names, and being static vs global, and having different - * addresses. Ditto ARMv7a and ARMv7m dummies. - */ - -static uint8_t arm11_gdb_dummy_fp_value[12]; - -static struct reg arm11_gdb_dummy_fp_reg = -{ - .name = "GDB dummy floating-point register", - .value = arm11_gdb_dummy_fp_value, - .dirty = 0, - .valid = 1, - .size = 96, - .arch_info = NULL, - .arch_type = 0, -}; - -static uint8_t arm11_gdb_dummy_fps_value[4]; - -static struct reg arm11_gdb_dummy_fps_reg = -{ - .name = "GDB dummy floating-point status register", - .value = arm11_gdb_dummy_fps_value, - .dirty = 0, - .valid = 1, - .size = 32, - .arch_info = NULL, - .arch_type = 0, -}; - - static int arm11_on_enter_debug_state(struct arm11_common *arm11); static int arm11_step(struct target *target, int current, uint32_t address, int handle_breakpoints); @@ -360,7 +328,7 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) int retval; FNC_INFO; - for (size_t i = 0; i < asizeof(arm11->reg_values); i++) + for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++) { arm11->reg_list[i].valid = 1; arm11->reg_list[i].dirty = 0; @@ -383,7 +351,7 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); } else { @@ -663,7 +631,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11) arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); } arm11_record_register_history(arm11); @@ -874,7 +842,7 @@ static int arm11_resume(struct target *target, int current, brp[1].address = ARM11_SC7_BCR0 + brp_num; brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); - arm11_sc7_run(arm11, brp, asizeof(brp)); + arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)); LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address); @@ -1117,7 +1085,7 @@ static int arm11_step(struct target *target, int current, brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); } - CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp))); + CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp))); /* resume */ @@ -1267,12 +1235,10 @@ static int arm11_get_gdb_reg_list(struct target *target, *reg_list_size = ARM11_GDB_REGISTER_COUNT; *reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT); + /* nine unused legacy FPA registers are expected by GDB */ for (size_t i = 16; i < 24; i++) - { - (*reg_list)[i] = &arm11_gdb_dummy_fp_reg; - } - - (*reg_list)[24] = &arm11_gdb_dummy_fps_reg; + (*reg_list)[i] = &arm_gdb_dummy_fp_reg; + (*reg_list)[24] = &arm_gdb_dummy_fps_reg; for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++) { @@ -1551,16 +1517,6 @@ static int arm11_bulk_write_memory(struct target *target, return arm11_write_memory(target, address, 4, count, buffer); } -/* here we have nothing target specific to contribute, so we fail and then the - * fallback code will read data from the target and calculate the CRC on the - * host. - */ -static int arm11_checksum_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t* checksum) -{ - return ERROR_FAIL; -} - /* target break-/watchpoint control * rw: 0 = write, 1 = read, 2 = access */ @@ -1672,13 +1628,13 @@ static int arm11_run_algorithm(struct target *target, if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } if (reg->size != reg_params[i].size) { LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - exit(-1); + return ERROR_INVALID_ARGUMENTS; } arm11_set_reg(reg,reg_params[i].value); // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val); @@ -1757,13 +1713,15 @@ static int arm11_run_algorithm(struct target *target, if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - exit(-1); + retval = ERROR_INVALID_ARGUMENTS; + goto del_breakpoint; } if (reg->size != reg_params[i].size) { LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - exit(-1); + retval = ERROR_INVALID_ARGUMENTS; + goto del_breakpoint; } buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32)); @@ -1854,7 +1812,7 @@ static int arm11_examine(struct target *target) arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0); arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1); - arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); @@ -1898,6 +1856,14 @@ static int arm11_examine(struct target *target) if (retval != ERROR_OK) return retval; + /* ETM on ARM11 still uses original scanchain 6 access mode */ + if (arm11->arm.etm && !target_was_examined(target)) { + *register_get_last_cache_p(&target->reg_cache) = + etm_build_reg_cache(target, &arm11->jtag_info, + arm11->arm.etm); + retval = etm_setup(target); + } + target_set_examined(target); return ERROR_OK; @@ -1943,6 +1909,11 @@ static int arm11_set_reg(struct reg *reg, uint8_t *buf) return ERROR_OK; } +static const struct reg_arch_type arm11_reg_type = { + .get = arm11_get_reg, + .set = arm11_set_reg, +}; + static int arm11_build_reg_cache(struct target *target) { struct arm11_common *arm11 = target_to_arm11(target); @@ -1951,12 +1922,6 @@ static int arm11_build_reg_cache(struct target *target) NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT); NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT); - if (arm11_regs_arch_type == -1) - arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg); - - register_init_dummy(&arm11_gdb_dummy_fp_reg); - register_init_dummy(&arm11_gdb_dummy_fps_reg); - arm11->reg_list = reg_list; /* Build the process context cache */ @@ -1974,11 +1939,11 @@ static int arm11_build_reg_cache(struct target *target) size_t i; /* Not very elegant assertion */ - if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) || - ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) || + if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) || + ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) || ARM11_REGCACHE_COUNT != ARM11_RC_MAX) { - LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX); + LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, ARRAY_SIZE(arm11->reg_values), ARRAY_SIZE(arm11_reg_defs), ARM11_RC_MAX); exit(-1); } @@ -1993,7 +1958,7 @@ static int arm11_build_reg_cache(struct target *target) r->value = (uint8_t *)(arm11->reg_values + i); r->dirty = 0; r->valid = 0; - r->arch_type = arm11_regs_arch_type; + r->type = &arm11_reg_type; r->arch_info = rs; rs->def_index = i; @@ -2005,16 +1970,16 @@ static int arm11_build_reg_cache(struct target *target) static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name) { - if (argc == 0) + if (CMD_ARGC == 0) { LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled"); return ERROR_OK; } - if (argc != 1) + if (CMD_ARGC != 1) return ERROR_COMMAND_SYNTAX_ERROR; - switch (args[0][0]) + switch (CMD_ARGV[0][0]) { case '0': /* 0 */ case 'f': /* false */ @@ -2052,11 +2017,11 @@ BOOL_WRAPPER(hardware_step, "hardware single step") COMMAND_HANDLER(arm11_handle_vcr) { - switch (argc) { + switch (CMD_ARGC) { case 0: break; case 1: - COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr); break; default: return ERROR_COMMAND_SYNTAX_ERROR; @@ -2131,56 +2096,14 @@ static int arm11_mcr(struct target *target, int cpnum, return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false); } -#define ARM11_HANDLER(x) .x = arm11_##x - -struct target_type arm11_target = { - .name = "arm11", - - ARM11_HANDLER(poll), - ARM11_HANDLER(arch_state), - - ARM11_HANDLER(target_request_data), - - ARM11_HANDLER(halt), - ARM11_HANDLER(resume), - ARM11_HANDLER(step), - - ARM11_HANDLER(assert_reset), - ARM11_HANDLER(deassert_reset), - ARM11_HANDLER(soft_reset_halt), - - ARM11_HANDLER(get_gdb_reg_list), - - ARM11_HANDLER(read_memory), - ARM11_HANDLER(write_memory), - - ARM11_HANDLER(bulk_write_memory), - - ARM11_HANDLER(checksum_memory), - - ARM11_HANDLER(add_breakpoint), - ARM11_HANDLER(remove_breakpoint), - ARM11_HANDLER(add_watchpoint), - ARM11_HANDLER(remove_watchpoint), - - ARM11_HANDLER(run_algorithm), - - ARM11_HANDLER(register_commands), - ARM11_HANDLER(target_create), - ARM11_HANDLER(init_target), - ARM11_HANDLER(examine), - - ARM11_HANDLER(mrc), - ARM11_HANDLER(mcr), - }; - - -int arm11_register_commands(struct command_context *cmd_ctx) +static int arm11_register_commands(struct command_context *cmd_ctx) { FNC_INFO; struct command *top_cmd, *mw_cmd; + armv4_5_register_commands(cmd_ctx); + top_cmd = register_command(cmd_ctx, NULL, "arm11", NULL, COMMAND_ANY, NULL); @@ -2212,5 +2135,48 @@ int arm11_register_commands(struct command_context *cmd_ctx) arm11_handle_vcr, COMMAND_ANY, "Control (Interrupt) Vector Catch Register"); - return ERROR_OK; + return etm_register_commands(cmd_ctx); } + +/** Holds methods for ARM11xx targets. */ +struct target_type arm11_target = { + .name = "arm11", + + .poll = arm11_poll, + .arch_state = arm11_arch_state, + + .target_request_data = arm11_target_request_data, + + .halt = arm11_halt, + .resume = arm11_resume, + .step = arm11_step, + + .assert_reset = arm11_assert_reset, + .deassert_reset = arm11_deassert_reset, + .soft_reset_halt = arm11_soft_reset_halt, + + .get_gdb_reg_list = arm11_get_gdb_reg_list, + + .read_memory = arm11_read_memory, + .write_memory = arm11_write_memory, + + .bulk_write_memory = arm11_bulk_write_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .add_breakpoint = arm11_add_breakpoint, + .remove_breakpoint = arm11_remove_breakpoint, + .add_watchpoint = arm11_add_watchpoint, + .remove_watchpoint = arm11_remove_watchpoint, + + .run_algorithm = arm11_run_algorithm, + + .register_commands = arm11_register_commands, + .target_create = arm11_target_create, + .init_target = arm11_init_target, + .examine = arm11_examine, + + .mrc = arm11_mrc, + .mcr = arm11_mcr, +};