X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2Fflash%2Fnor%2Fcfi.c;h=62d2ae4989190522f2126d76ddd98a3b7e2afef7;hb=9933fa334de551096674d4044ed7ac2152213e8b;hp=f854dd632b459595134f7a024ac645b3bdfc130c;hpb=6e5c37be29cdefc0ea2de6d06866811bc7e44cbd;p=openocd.git diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c index f854dd632b..62d2ae4989 100644 --- a/src/flash/nor/cfi.c +++ b/src/flash/nor/cfi.c @@ -65,6 +65,7 @@ static const struct cfi_fixup cfi_0002_fixups[] = { {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, + {CFI_MFR_SST, 0x274b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]}, {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL}, {CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */ @@ -72,6 +73,7 @@ static const struct cfi_fixup cfi_0002_fixups[] = { {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]}, {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]}, {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]}, + {CFI_MFR_EON, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]}, {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]}, {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL}, {CFI_MFR_ST, 0x227E, cfi_fixup_0002_write_buffer, NULL}, /* M29W128G */ @@ -766,7 +768,7 @@ static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size) buf += printed; buf_size -= printed; - printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n", + snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n", (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f, (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f); @@ -800,7 +802,7 @@ static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size) buf += printed; buf_size -= printed; - printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, " + snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, " "factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size); @@ -1220,7 +1222,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, struct target *target = bank->target; struct reg_param reg_params[7]; struct arm_algorithm armv4_5_info; - struct working_area *source; + struct working_area *source = NULL; uint32_t buffer_size = 32768; uint32_t write_command_val, busy_pattern_val, error_pattern_val; @@ -1895,13 +1897,15 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, armv4_5_info.common_magic = ARMV7M_COMMON_MAGIC; armv4_5_info.core_mode = ARMV7M_MODE_HANDLER; armv4_5_info.core_state = ARM_STATE_ARM; - } - else + } else if (armv4_5_info.common_magic == ARM_COMMON_MAGIC) { /* All other ARM CPUs have 32 bit instructions */ armv4_5_info.common_magic = ARM_COMMON_MAGIC; armv4_5_info.core_mode = ARM_MODE_SVC; armv4_5_info.core_state = ARM_STATE_ARM; + } else { + LOG_ERROR("Unknown ARM architecture"); + return ERROR_FAIL; } int target_code_size = 0; @@ -1910,11 +1914,12 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, switch (bank->bus_width) { case 1 : - if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) /* armv4_5 target */ - { - target_code_src = armv4_5_word_8_code; - target_code_size = sizeof(armv4_5_word_8_code); + if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) { + LOG_ERROR("Unknown ARM architecture"); + return ERROR_FAIL; } + target_code_src = armv4_5_word_8_code; + target_code_size = sizeof(armv4_5_word_8_code); break; case 2 : /* Check for DQ5 support */ @@ -1934,19 +1939,21 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, else { /* No DQ5 support. Use DQ7 DATA# polling only. */ - if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) // armv4_5 target - { - target_code_src = armv4_5_word_16_code_dq7only; - target_code_size = sizeof(armv4_5_word_16_code_dq7only); + if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) { + LOG_ERROR("Unknown ARM architecture"); + return ERROR_FAIL; } + target_code_src = armv4_5_word_16_code_dq7only; + target_code_size = sizeof(armv4_5_word_16_code_dq7only); } break; case 4 : - if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) // armv4_5 target - { - target_code_src = armv4_5_word_32_code; - target_code_size = sizeof(armv4_5_word_32_code); + if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) { + LOG_ERROR("Unknown ARM architecture"); + return ERROR_FAIL; } + target_code_src = armv4_5_word_32_code; + target_code_size = sizeof(armv4_5_word_32_code); break; default: LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width); @@ -2702,6 +2709,7 @@ static int cfi_probe(struct flash_bank *bank) } cfi_info->probed = 0; + cfi_info->num_erase_regions = 0; if (bank->sectors) { free(bank->sectors); @@ -3149,7 +3157,7 @@ static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size) if (cfi_info->qry[0] == 0xff) { - printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n"); + snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n"); return ERROR_OK; }