# SPDX-License-Identifier: GPL-2.0-or-later # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ # # Texas Instruments K3 devices: # * AM654x: https://www.ti.com/lit/pdf/spruid7 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3 # * J721E: https://www.ti.com/lit/pdf/spruil1 # Has 2 ARMV8 Cores and 6 R5 Cores and an M3 # * J7200: https://www.ti.com/lit/pdf/spruiu1 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3 # * AM642: https://www.ti.com/lit/pdf/spruim2 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3 # if { [info exists SOC] } { set _soc $SOC } else { set _soc am654 } # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug if { [info exists V8_SMP_DEBUG] } { set _v8_smp_debug $V8_SMP_DEBUG } else { set _v8_smp_debug 0 } # Common Definitions # System Controller is the very first processor - all current SoCs have it. set CM3_CTIBASE {0x3C016000} # sysctrl power-ap unlock offsets set _sysctrl_ap_unlock_offsets {0xf0 0x44} # All the ARMV8s are the next processors. # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000} set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000} # And we add up the R5s # (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000} set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000} set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1} # Finally an General Purpose(GP) MCU set CM4_CTIBASE {0x20001000} # General Purpose MCU (M4) may be present on some very few SoCs set _gp_mcu_cores 0 # General Purpose MCU power-ap unlock offsets set _gp_mcu_ap_unlock_offsets {0xf0 0x60} # Set configuration overrides for each SOC switch $_soc { am654 { set _CHIPNAME am654 set _K3_DAP_TAPID 0x0bb5a02f # AM654 has 2 clusters of 2 A53 cores each. set _armv8_cpu_name a53 set _armv8_cores 4 # AM654 has 1 cluster of 2 R5s cores. set _r5_cores 2 set _mcu_r5_cores 2 set _main0_r5_cores 0 set _main1_r5_cores 0 set R5_NAMES {mcu_r5.0 mcu_r5.1} # Sysctrl power-ap unlock offsets set _sysctrl_ap_unlock_offsets {0xf0 0x50} } am642 { set _CHIPNAME am642 set _K3_DAP_TAPID 0x0bb3802f # AM642 has 1 clusters of 2 A53 cores each. set _armv8_cpu_name a53 set _armv8_cores 2 set ARMV8_DBGBASE {0x90010000 0x90110000} set ARMV8_CTIBASE {0x90020000 0x90120000} # AM642 has 2 cluster of 2 R5s cores. set _r5_cores 4 set _mcu_r5_cores 0 set _main0_r5_cores 2 set _main1_r5_cores 2 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1} set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000} set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000} # M4 processor set _gp_mcu_cores 1 } j721e { set _CHIPNAME j721e set _K3_DAP_TAPID 0x0bb6402f # J721E has 1 cluster of 2 A72 cores. set _armv8_cpu_name a72 set _armv8_cores 2 # J721E has 3 clusters of 2 R5 cores each. set _r5_cores 6 set _mcu_r5_cores 2 set _main0_r5_cores 2 set _main1_r5_cores 2 } j7200 { set _CHIPNAME j7200 set _K3_DAP_TAPID 0x0bb6d02f # J7200 has 1 cluster of 2 A72 cores. set _armv8_cpu_name a72 set _armv8_cores 2 # J7200 has 2 clusters of 2 R5 cores each. set _r5_cores 4 set _mcu_r5_cores 2 set _main0_r5_cores 2 set _main1_r5_cores 0 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000} set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000} # M3 CTI base set CM3_CTIBASE {0x20001000} } default { echo "'$_soc' is invalid!" } } jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu set _TARGETNAME $_CHIPNAME.cpu set _CTINAME $_CHIPNAME.cti # sysctrl is always present cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0] target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine $_TARGETNAME.sysctrl configure -event reset-assert { } proc sysctrl_up {} { # To access sysctrl, we need to enable the JTAG access for the same. # Ensure Power-AP unlocked $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098 $::_TARGETNAME.sysctrl arp_examine } $_TARGETNAME.sysctrl configure -event gdb-attach { sysctrl_up # gdb-attach default rule halt 1000 } set _v8_smp_targets "" for { set _core 0 } { $_core < $_armv8_cores } { incr _core } { cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \ -baseaddr [lindex $ARMV8_CTIBASE $_core] target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \ -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core" } # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs set _armv8_up_cmd "$_armv8_cpu_name"_up # Available if V8_SMP_DEBUG is set to non-zero value set _armv8_smp_cmd "$_armv8_cpu_name"_smp if { $_v8_smp_debug == 0 } { proc $_armv8_up_cmd { args } { foreach { _core } [set args] { $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit } } } else { proc $_armv8_smp_cmd { args } { for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } { $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on } # Set Default target are core 0 targets $::_TARGETNAME.$::_armv8_cpu_name.0 } # Declare SMP target smp $:::_v8_smp_targets } for { set _core 0 } { $_core < $_r5_cores } { incr _core } { set _r5_name [lindex $R5_NAMES $_core] cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \ -baseaddr [lindex $R5_CTIBASE $_core] # inactive core examination will fail - wait till startup of additional core target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \ -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine } if { $_mcu_r5_cores != 0 } { proc mcu_r5_up { args } { foreach { _core } [set args] { $::_TARGETNAME.mcu_r5.$_core arp_examine $::_TARGETNAME.mcu_r5.$_core cortex_r4 dbginit } } } if { $_main0_r5_cores != 0 } { proc main0_r5_up { args } { foreach { _core } [set args] { $::_TARGETNAME.main0_r5.$_core arp_examine $::_TARGETNAME.main0_r5.$_core cortex_r4 dbginit } } } if { $_main1_r5_cores != 0 } { proc main1_r5_up { args } { foreach { _core } [set args] { $::_TARGETNAME.main1_r5.$_core arp_examine $::_TARGETNAME.main1_r5.$_core cortex_r4 dbginit } } } if { $_gp_mcu_cores != 0 } { cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0] target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine $_TARGETNAME.gp_mcu configure -event reset-assert { } proc gp_mcu_up {} { # To access GP MCU, we need to enable the JTAG access for the same. # Ensure Power-AP unlocked $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098 $::_TARGETNAME.gp_mcu arp_examine } $_TARGETNAME.gp_mcu configure -event gdb-attach { gp_mcu_up # gdb-attach default rule halt 1000 } }