# SPDX-License-Identifier: GPL-2.0-or-later
# Cadence virtual debug interface
# Arm Cortex A53x2 through DAP

source [find interface/vdebug.cfg]

set CORES 4
set CHIPNAME a75
set ACCESSPORT 0x00040000
set MEMSTART 0x00000000
set MEMSIZE 0x1000000
set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
set CPUTAPID 0x4ba06477

# vdebug select transport
transport select jtag

# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
adapter speed 1500000
adapter srst delay 5

# BFM hierarchical path and input clk period
vdebug bfm_path tbench.u_vd_jtag_bfm 333ps

jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
jtag arp_init-reset

source [find target/vd_aarch64.cfg]